Tester for semiconductor devices and test tray used for the same

ABSTRACT

An IC tester which is capable of reducing the time required before completion of testing on all of ICs to be tested is provided. The depth (length in the Y-axis direction) of the constant temperature chamber  4  and the exit chamber  5  is expanded by a dimension corresponding approximately to one transverse width (length of the minor edge) of the rectangular test tray  3 , and two generally parallel test tray transport paths or alternatively a widened test tray transport path broad enough to transport two test trays simultaneously with the two test trays juxtaposed in a direction transverse to the widened test tray transport path are provided in the section of test tray transport path extending from the soak chamber  41  in the constant temperature chamber  4  through the testing section  42  in the constant temperature chamber  4  to the exit chamber  5  so that two test trays may be simultaneously transported along the two test tray transport paths or the widened test tray transport path.

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device testingapparatus suitable for testing semiconductor integrated circuit elementswhich are typical of semiconductor devices, and more particularly to asemiconductor device testing apparatus of the type in whichsemiconductor devices are transported to a testing section or testsection where they are tested for their electrical characteristics,followed by being carried out of the test section and then being sortedout into conforming articles and non-conforming articles on the basis ofthe test results, and to a test tray for use in the IC tester which atray is moved in a circulating manner along a predetermined path oftransport.

BACKGROUND ART

[0002] Many of semiconductor device testing apparatuses (commonly calledIC tester) for measuring the electrical characteristics of semiconductordevices to be tested (commonly called DUT (device under test)) byapplying a signal of a predetermined test pattern to the devices have asemiconductor transporting and handling (processing) apparatus (commonlycalled handler) integrally incorporated therein for transportingsemiconductor devices to a testing section where they are brought intoelectrical contact with device sockets on the tester head of the testingapparatus (a component of the testing apparatus for supplying andreceiving various electrical signals for testing purposes), followed bycarrying the tested semiconductor devices out of the testing section andsorting them out into conforming and non-conforming articles on thebasis of the test results. The semiconductor device testing apparatushaving integrated therein the handler of the type described above isherein termed simply “IC tester”. In the following disclosure thepresent invention will be described by taking semiconductor integratedcircuit elements (which will be referred to as IC hereinafter) which aretypical of semiconductor devices by example for the convenience ofexplanation.

[0003] First, the general construction one example of the prior artsemiconductor device testing apparatus (which will be referred to as ICtester hereinafter) will be described with reference to FIG. 11.

[0004]FIG. 11 is a plan view illustrating the general construction ofthe IC tester with a plurality of test trays 3 within a soak chamber 41and an exit chamber 5 shown in a perspective view. In addition to aconstant temperature chamber 4 including the soak chamber 41 and atesting section 42, and the exit chamber 5 (also known asheat-removal/cold-removal chamber), the illustrated IC tester comprisesa storage section 11 for storing universal trays (also known as customertrays) 1 loaded with ICs to be tested and universal trays 1 loaded withICs already tested and sorted, a loader section 7 where ICs being testedare transferred from the universal trays (customer trays) 1 and reloadedonto a test tray 3, and an unloader section 8 where the tested ICs whichhave been carried on the test tray 3 out through the exit chamber 5subsequently to undergoing a test in the testing section 42 of theconstant temperature chamber 4 are transferred from the test tray 3 tothe universal tray 1 to be reloaded on the latter. The unloader section8 is generally configured to sort tested ICs based on the data of thetest results and load them on the corresponding universal trays.

[0005] The soak chamber 41 of the constant temperature chamber 4 isdesigned for imposing temperature stresses of either a predeterminedhigh or low temperature on ICs under test loaded on a test tray 3 in theloader section 7 while the testing section 42 is designed for executingelectrical tests on the ICs under the predetermined temperature stressimposed in the soak chamber 41. In order to maintain the ICs loaded withtemperature stresses of either a predetermined high or low temperaturein that temperature during the test, the soak chamber 41 and testingsection 42 are both contained in the constant temperature chamber 4capable of maintaining the interior atmosphere at a predeterminedtemperature.

[0006] The illustrated IC tester is configured such that the soakchamber 41 and testing section 42 of the constant temperature chamber 4and the exit chamber 5 are arranged in the order named from left toright as viewed in the drawing (referred to as X-axis direction herein)while the loader section 7 and unloader section 8 are located in frontof the constant temperature chamber 4 and the exit chamber 5 (downwardin the upward-downward direction as viewed in the drawing (referred toas Y-axis direction herein) which is perpendicular to the X-axisdirection). As is apparent from FIG. 11, the loader section 7 is locatedin front of the soak chamber 41 of the constant temperature chamber 4while the unloader section 8 is located in front of the testing section42 and the exit chamber 5.

[0007] The test tray 3 is moved in a circulating manner from and back tothe loader section 7 sequentially through the soak chamber 41 and thetesting section 42 in the constant temperature chamber 4, the exitchamber 5, and the unloader section 8. In this path of circulatingtravel, there are disposed a predetermined number of test trays 3 whichare successively moved in the directions as indicated by thickcross-hatched arrows in FIG. 11 by a test tray transport, not shown.

[0008] A test tray 3, loaded with ICs being tested in the loader section7, is conveyed from the loader section to the constant temperaturechamber 4, and then delivered to the soak chamber 41 through an inletport formed in the front wall of the constant temperature chamber 4. Thesoak chamber 41 is equipped with a vertical transport mechanism which isconfigured to support a plurality of (say, 5) test trays 3 in the formof a stack with predetermined spacings between successive trays. In theillustrated example, a test tray newly received from the loader section7 is supported at the top of the stack while the lowermost test tray isdelivered to the testing section 42 which on the left-hand side(upstream side) in the X-axis direction, adjoins and communicates withthe lower portion of the soak chamber 41. It is thus to be appreciatedthat test trays 3 are delivered out in the direction perpendicular tothat in which they have been introduced.

[0009] ICs being tested are loaded with either a predetermined high orlow temperature stress as the associated test tray 3 is movedsequentially from the top to the bottom of the stack by vertically(which is referred to as Z-axis direction) downward movement of thevertical transport mechanism and during a waiting period until thetesting section 42 is emptied. In the testing section 42 there islocated a tester head, not shown. The test tray 3 which has been carriedone by one out of the constant temperature chamber 4 is placed onto thetester head where a predetermined number of ICs out of the ICs undertest loaded on the test tray are brought into electrical contact withdevice sockets (not shown) mounted on the tester head. Upon completionof the test on all of the ICs placed on one test tray through the testerhead, the test tray 3 is conveyed to the right side (downstream) in theX-axis direction to the exit chamber 5 where the tested ICs are relievedof heat or cold.

[0010] Like the soak chamber 41 as described above, the exit chamber 5is also equipped with a vertical transport mechanism adapted to supporta plurality of (say, five) test trays 3 stacked one on another withpredetermined spacings therebetween. In the illustrated example, a testtray newly received from the testing section 42 is supported at thebottom of the stack while the uppermost test tray is discharged to theunloader section 8. The tested ICs are relieved of heat or cold to berestored to the outside temperature (room temperature) as the associatedtest tray 3 is moved sequentially from the bottom to the top of thestack by vertically upward movement of the vertical transport mechanism.

[0011] Since the IC test is typically conducted on ICs having a desiredtemperature stress in a wide range of temperatures from −55° C. to +125°C. imposed thereon in the soak chamber 41, the exit chamber 5 cools theICs with forced air down to the room temperature if the ICs have had ahigh temperature of, say, about 120° C. applied thereto in the soakchamber 41. If ICs have had a low temperature of, say, about −30° C.applied thereto in the soak chamber 41, the exit chamber 5 heats themwith heated air or a heater up to a temperature at which no condensationoccurs. In addition, since a test tray 3 on which ICs to be tested areloaded is exposed to such wide range of temperatures, there is usuallyused the test tray 3 formed of a material capable of withstanding a hightemperature such as 125° C. and a low temperature such as −55° C.However, there are many cases that the IC test is conducted on ICshaving the normal temperature or room temperature, and in such cases thetest tray 3 need not be formed of a material capable of withstandingsuch high/low temperatures.

[0012] After the heat removal or cold removal process, the test tray 3is conveyed in the direction (facing on the front of the exit chamber 5)perpendicular to that in which it has been introduced from the testingsection 42 prior to being discharged from the exit chamber 5 to theunloader section 8.

[0013] The unloader section 8 is configured to sort the tested ICscarried on the test tray 3 by categories based on the data of the testresults and transfer them onto the corresponding universal trays. Inthis example, the unloader section 8 provides for stopping the test tray3 at two positions A and B. The ICs on the test trays 3 stopped at thefirst position A and the second position B are sorted out based on thedata of the test results and transferred onto and stored in theuniversal trays of the corresponding categories at rest at the universaltray set positions (stop positions) 1 2, four universal trays 1 a, 1 b,1 c and 1 d in the example illustrated.

[0014] The test tray 3 emptied in the unloader section 8 is deliveredback to the loader section 7 where it is again loaded with ICs beingtested from the universal tray 1 to repeat the same steps of operation.

[0015]FIG. 12 shows the construction of one example of the test tray 3.The test tray 3 comprises a rectangular frame 30 having a plurality ofequally spaced apart parallel cleats 31 between the opposed side framemembers 30 a and 30 b of the frame, each of the cleats 31 having aplurality of equally spaced apart mounting lugs 36 protruding therefromon both sides thereof and each of the side frame members 30 a, 30 bopposing the adjacent cleats having similar mounting lugs 36 protrudingtherefrom. The mounting lugs 36 protruding from the opposed sides ofeach of the cleats 31 are arranged such that each of the mounting lugs36 protruding from one side of the cleat 31 is positioned intermediatetwo adjacent mounting lugs 36 protruding from the opposite side of thecleat. Similarly, each of the mounting lugs 36 protruding from each ofthe side frame members 30 a and 30 b is positioned intermediate twoadjacent mounting lugs 36 protruding from the opposed cleat. Formedbetween each pair of opposed cleats 31 and between each of the sideframe members 30 a and 30 b and the opposed cleats are spaces foraccommodating a multiplicity of IC carriers 34 in juxtaposition. Morespecifically, each IC carrier 34 is accommodated in one of an array ofrectangular carrier compartments 37 defined in each of said spaces, eachcompartment 37 including two staggered, obliquely opposed mounting lugs36 located at the diagonally opposed corners of the compartment. In theillustrated example wherein each cleat 31 has sixteen mounting lugs 36on either side thereof, there are sixteen carrier compartments 37 formedin each of said spaces, in which sixteen IC carriers 34 are mounted.Since there are four of the spaces, 16×4, that is, 64 IC carriers intotal can be mounted in one test tray 3. Each IC carrier 34 is affixedto two mounting lugs 36 by fasteners 35.

[0016] Each of IC carriers 34 is of identical shape and size in itsouter contour and has an IC pocket 38 in the center for accommodating anIC device therein. The shape of the IC pocket 38 of each IC carrier 34is determined depending on that of the IC device to be accommodatedtherein. In the illustrated example the IC pocket 38 is in the shape ofa generally square recess. The outer dimensions of the IC carrier 34 aresized so as to be loosely fitted in the space defined between theopposed mounting lugs 36 in the carrier compartment 37. The IC carrier34 has flanges at its opposed ends adapted to rest on the correspondingmounting lugs 36, these flanges being formed therethrough with mountingholes 39 for receiving fasteners 35 therethrough and holes 40 forpassing locating pins therethrough.

[0017] Since the test tray 3 is exposed to a wide range of temperaturesfrom −55° C. to +125° C. in the constant temperature chamber 4, it isrequired that the test tray 3 be constructed of a material capable ofwithstanding a high temperature of, say, about 120° C. and a lowtemperature of, say, about −30° C. In this example, the rectangularframe 30, the cleats 31 and the mounting lugs 36 are constructed ofaluminum alloy while the IC carrier 34 is made of insulating syntheticresin.

[0018] In this example, as shown in FIG. 11, the IC transport fortransferring ICs from the universal tray 1 to the test tray 3 in theloader section 7 may be in the form of X-Y-axis direction transport 71comprising a pair of opposed parallel rails 71A, 71B mounted over theloader section 7 at the ends thereof opposed in the X-axis direction andextending in the Y-axis direction, a movable arm 71C spanning andmounted at opposite ends on the pair of rails 71A, 71B for movement inthe Y-axis direction, and a movable head, not shown (which is known inthe art concerned as pick-and-place head) mounted on the movable arm 71Cfor movement therealong longitudinally of the arm, that is, in theX-axis direction. With this construction, the movable head isreciprocally movable in the Y-axis direction between the test tray 3 andthe universal tray 1 as well as in the X-axis direction along themovable arm 71C.

[0019] The movable head has an IC pick-up pad (IC grasping member)vertically movably mounted on its bottom surface. The movement of themovable head in the X-Y-axis directions and the downward movement of thepick-up pad bring the pick-up pad into abutment with the ICs placed onthe universal tray 1 at rest at the universal tray set position 12 toattract and grasp them by vacuum suction, for instance for transfer fromthe universal tray 1 to the test tray 3. The movable head may beprovided with a plurality of, say, eight pick-up pads so that eight ICsat a time may be transported from the universal tray 1 to the test tray3.

[0020] It is to be noted here that a position corrector 2 for correctingthe orientation or position of an IC called “preciser” is locatedbetween the universal tray set position 12 and the stop position for thetest tray 3. The IC position corrector or preciser 2 includes relativelydeep recesses into which ICs as being attracted against the pick-up padsare released to fall down prior to being transferred to the test tray 3.The recesses are each bounded by vertical tapered side walls whichprescribe for the depth to which the ICs drop into the recesses byvirtue of the tapering. Once eight ICs have been positioned relative toeach other by the position corrector 2, those accurately positioned ICsare again attracted against the pick-up pads and transferred to the testtray 3. The universal tray 1 is provided with recesses for holding ICswhich are oversized as compared to the size of ICs, resulting in widevariations in positions of ICs stored in the universal tray 1.Consequently, if the ICs as such were grasped by the pick-up pads andtransferred directly to the test tray 3, there might be some of themwhich could not be successfully deposited into the IC storage recessesin the test tray 3. This is the reason for requiring the positioncorrector 2, as described above which acts to array ICs as accurately asthe array of the IC storage recesses in the test tray 3.

[0021] The unloader section 8 is equipped with an X-Y transport 81 whichis identical in construction to the X-Y transport 71 provided for theloader section 7. The X-Y transport 81 is mounted spanning the firstposition A and the second position B and performs to transship thetested ICs from the test tray 3 delivered out to the unloader section 8onto the corresponding universal tray 1. The X-Y transport 81 comprisesa pair of spaced parallel rails 81A, 81B mounted over the unloadersection 8 at the ends thereof opposed in the X-axis direction andextending in the Y-axis direction, a movable arm 81C spanning andmounted at opposite ends on the pair of rails 81A, 81B for movement inthe Y-axis direction, and a movable head, not shown mounted on themovable arm 71C for movement therealong longitudinally of the arm, thatis, in the X-axis direction.

[0022] The sorting operation in the unloader section 8 will now bedescribed. In the IC tester shown in FIG. 11, the operation of sortingand transshipping tested ICs is performed with respect to only universaltrays arranged adjacent to each of the first and second positions A andB. Specifically, arranged at the first position A are universal trays 1a and 1 b. Let it assume that classification categories 1 and 2 areassigned to the universal trays 1 a and 1 b, respectively, while thetest tray 3 is stopped at the first position A, only the tested ICsbelonging to the categories 1 and 2 are picked up from the test tray andtransferred onto the corresponding universal trays 1 a and 1 b,respectively. Once the test tray 3 stopping at the first position A hasbeen depleted of the ICs belonging to the categories 1 and 2, the testtray is moved to the second position B.

[0023] Arranged at and in opposing relation to the second position B areuniversal trays 1 c and 1 d. Assuming that classification categories 3and 4 are allotted to these universal trays 1 c and 1 d, respectively,the tested ICs belonging to the categories 3 and 4 are picked up fromthe test tray 3 held at the second position B, and transferred onto thecorresponding universal trays 1 c and 1 d, respectively. While thesorting is being carried out at the second position B, the next testtray 3 is delivered from the exit chamber 5 to the unloader section 8and is stopped at the first position A in preparation for the sortingoperation.

[0024] The distance for the X-Y transport 81 required to travel for thesorting operation can be reduced by the arrangement described above inwhich the X-Y transport 81 is shared by the two unloader sections(represented by the first and second positions A and B) and in which thesorting operations are limited to the universal trays 1 a, 1 b anduniversal trays 1 c, 1 d closest to the test tray stop positions A andB, respectively. It is thus to be understood that this constructionpermits the overall processing time required for the sorting to beshortened, despite the fact that the single X-Y transport 81 is used forthe sorting operation.

[0025] It should be noted here that the number of universal trays 1 thatcan be installed at the universal tray set positions 12 in the unloadersection 8 is limited to four by the space available in this example.Hence, the number of categories into which ICs can be sorted in realtime operation is limited to four categories 1 to 4 as noted above.While four categories would generally be sufficient to cover threecategories for subclassifying “conforming articles” into high, mediumand low response speed elements in addition to one category allotted to“non-conforming article,” in some instances there may be some among thetested ICs which do not belong to any of these categories. Should therebe found any tested ICs which should be classified into a category otherthan the four categories, a universal tray 1 assigned to the additionalcategory should be taken from the IC storage section 11 and betransported into the unloader section 8 to store the ICs of theadditional category. In doing that, it would be needed to transport anyone of the universal trays positioned in the unloader section 8 to theIC storage section 11 for storage therein.

[0026] If the replacement of the universal trays is effected in thecourse of the sorting operation, the latter operation would have to beinterrupted during the replacement. For this reason, in this example abuffer section 6 is disposed between the stop positions A and B for thetest tray 3 and the locations of the universal trays 1 a-1 d. The buffersection 6 is configured to temporarily keep tested ICs belonging to acategory of rare occurrence.

[0027] The buffer section 6 may have a capacity of accommodating, sayabout twenty to thirty ICs and be equipped with a memory portion forstoring the category of ICs placed in IC pockets of the buffer section6. The locations and category of the individual ICs temporarily kept inthe buffer section 6 are thus stored in the memory portion. Between thesorting operations or upon the buffer section 6 being filled with ICs, auniversal tray for the category to which the ICs kept in the buffersection belong is carried from the IC storage section 11 to the unloadersection 8 to receive the ICs. It should be noted that ICs temporarilykept in the buffer section 6 may be scattered over a plurality ofcategories. In that case, it would be required to transport as manyuniversal trays as the number of categories at a time from the ICstorage section 11 to the unloader section 8.

[0028] The IC carrier 34 holds an 18 in place with its leads or pins PNexposed downwardly as shown in FIG. 13. The tester head 100 is providedwith an IC socket having contacts 101 extending upwardly from the topsurface thereof. The exposed pins PN of the IC are urged against thecontacts 101 of the IC socket to establish electrical connection betweenthe IC and the socket. To this end, a pusher 103 for pushing and holdingan IC down is mounted above the tester head and is configured to pushthe IC accommodated in an IC carrier 34 from above to bring the pins PNinto contact with the tester head.

[0029] The number of ICs which may be tested at a time with the testerhead depends on the number of IC sockets mounted on the tester head. Byway of example, where sixty-four ICs are carried in an array of 4lines×16 rows on a test tray 3 as shown in FIG. 14, 4×4, that is, 16 ICsockets are arranged and mounted on the tester head such that the ICs(shown as cross-hatched) in every fourth row in each of the lines may betested all at once. More specifically, in the first test run theexamination is conducted on sixteen ICs located in the first, fifth,ninth and thirteenth rows in each line, the second test run is effectedon another sixteen ICs located in the second, sixth, tenth andfourteenth rows in each line by shifting the test tray 3 by a distancecorresponding to one row of ICs, and the third and fourth test runs arecarried out in the similar manner until all of the ICs are tested. Thetest results are stored in a memory with the addresses determined by theidentification number affixed to the test tray 3 and the IC numbersassigned to the ICs contained in the test tray, for example. It is to beappreciated that where thirty-two IC sockets may be mounted on thetester head, only two test runs are required to examine all sixty-fourICs arranged in an array of 4 lines×16 rows.

[0030] The IC storage section 11 comprises two, in this example,IC-to-be-tested storage racks (not shown) for accommodating universaltrays 1 loaded with ICs being tested and seven, in this example,tested-IC storage racks (not shown) for accommodating universal trays 1loaded with tested ICs sorted out by categories on the basis of the testresults. The IC-to-be-tested storage rack and tested-IC storage rack areconfigured to accommodate universal trays in the form of a stack. Theuniversal trays 1 with ICs under test carried thereon stored in the formof a stack in the IC-to-be-tested storage rack are transportedsuccessively from the top of the stack to the loader section 7 where theICs being tested are transferred from the universal trays 1 onto testtrays 3 on standby in the loader section 7.

[0031] Each of the IC-to-be-tested storage rack and tested-IC storagerack one of which is shown in FIG. 15 comprises a tray supporting frame51 open at the top and having an opening at the bottom, and an elevator52 disposed below the tray supporting frame 51 so as to be verticallymovable through the bottom opening thereof. In the tray supporting frame51 there are stored and supported a plurality of universal trays 1stacked one on another which are vertically moved by the elevator 52acting through the bottom opening of the tray supporting frame 51.

[0032] A tray transport, although not shown in FIG. 11, is disposedabove the IC-to-be-tested storage racks and the tested-IC storage racksfor movement over the entire extent of those storage racks in thedirection of arrangement of the racks (in the X-axis direction). Thetray transport is provided on its bottom with grasp means for grasping auniversal tray 1. The tray transport is moved to a position over theIC-to-be-tested storage rack whereupon the elevator 52 is actuated tolift the universal trays 1 stacked in the IC-to-be-tested storage rack,so that the uppermost universal tray 1 may be engaged and grasped by thegrasp means of the tray transport. Once the uppermost universal tray 1loaded with ICs being tested has been transferred to the tray transport,the elevator 52 is lowered to its original position. The tray transportis then horizontally moved to and stopped at a position underlying theuniversal tray set position 12 in the loader section 7 where the traytransport has its grasp means release the universal tray 1 to allow itto drop into an immediately underlying tray receiver (not shown). Thetray transport having the universal tray 1 unloaded therefrom is movedout of the loader section 7. Then, the elevator (not shown) is movedupward from below the tray receiver having the universal tray 1 placedthereon to lift up the universal tray 1 loaded with ICs to be tested sothat the universal tray 1 is held at the universal tray set position 12.

[0033] In the unloader section 8 as well, four empty universal trays arepositioned and held at the respective universal tray set positions 12 bythe tray transport described above, the tray receivers and associatedelevators. Once one universal tray 1 has been fully filled, theuniversal tray is lowered from the set position 12 by the elevator, andis subsequently stored in the tray storage position assigned to thatparticular tray by the tray transport.

[0034] The length of the testing time (also called measuring time)required for the IC tester to test ICs significantly varies dependingupon the type of the IC and the contents of the test. Generally, onetest takes about a few seconds to several tens of minutes as measuredafter an IC carried into the testing section 42 as loaded on a test trayhas been brought into contact with an IC socket.

[0035] In testing ICs in the testing section 42, a relatively long timerequired per a test necessitates a corresponding long waiting time untilan IC carried into the soak chamber 41 as loaded on a test tray comes upfor testing in the testing section 42, meaning that the test traytransporting mechanism need not be so fast in operation. In addition,the number of test trays to be stacked in the soak chamber 41 can bereduced.

[0036] This, however, requires a very long time to go through the teston all of the ICS, leading to a poor utilization ratio of the expensiveIC tester and hence the serious disadvantage that the testing cost peran IC is greatly an increased.

[0037] In order to alleviate this disadvantage, it is required toincrease the number of ICs which can be simultaneously tested (ormeasured) in the testing section 42 (which is called simultaneousmeasurement throughput in number of ICs). However, there is a limit tothe number of IC sockets which can be mounted on a tester head, which inturn imposes a limit on the increase in simultaneous measurementthroughput in number of ICs.

[0038] In addition, an increase in simultaneous measurement throughputin number of ICs in number of ICs for simultaneous measurement wouldrequire the number of ICs which can be handled by the transporting andhandling mechanism including the X-Y transports 71 and 81 for the loadersection 7 and the unloader section 8, respectively. While the throughputin number of ICs depends on the performance or throughput capacity ofthis transporting and handling mechanism, in the case that the testingtime is relatively long, there would be no particular problem if thethroughput in number of ICs was not increased so much.

[0039] In contrast, in the case that the testing time in the testingsection 42 is relatively short, failure to transport test trays to thetesting section 42 at high speed would involve a longer lost time in thetesting operation in the testing section 42, resulting in undesirablyprolonging the working time of the IC tester. Accordingly, fastoperation is required of the test tray transporting mechanism. Further,it is preferable that the number of test trays which can be stacked inthe soak chamber 41 be larger.

[0040] However, although it would not take much cost to make theoperation of the test tray transporting mechanism only to a limitedextent, it would require substantial cost to increase the operationspeed to nearly the maximal limit, providing the disadvantage ofrendering he initial cost of the entire IC tester very expensive. On topof that, in order to transport test trays at high speed, it is requiredto increase the throughput in number of ICs of the transporting andhandling mechanism including the X-Y transports 71 and 81. Not only isit costly to increase the throughput in number of ICs, but also is therenaturally a limit to increasing the throughput in number of ICs. Itshould also be noted that when the testing time in the testing section42 is relatively short, increasing the simultaneous measurementthroughput in number of ICs would not lead to a significant enhancementof efficiency.

DISCLOSURE OF THE INVENTION

[0041] A first object of the present invention is to provide an ICtester which is capable of reducing the time required before completionof testing on all of the ICs to thereby enhance the utilization ratio.

[0042] A second object of the present invention is to provide an ICtester which is capable of transporting test trays from the soak chamberthrough the testing section to the exit chamber and which provides anenhanced simultaneous measurement throughput in number of ICs.

[0043] A third object of the present invention is to provide an ICtester which provides an increased throughput in number of ICs throughthe loader and unloader sections to thereby shorten the time requiredbefore completion of testing on all of the ICs to be tested.

[0044] A fourth object of the present invention is to provide a testtray for use in an IC tester which provides for transporting test traysfrom the soak chamber through the testing section to the exit chamber inan efficient manner.

[0045] In order to accomplish the foregoing objects, according to afirst aspect of the present invention, in a semiconductor device testingapparatus of the type in which semiconductor devices, loaded on a testtray, are transported to a testing section where the semiconductordevices while loaded on the test tray are tested and after completion ofthe testing, are carried out of the testing section, followed by beingsorted out on the basis of the test results, a semiconductor devicetesting apparatus is provided in which a plurality of transport pathsare provided for transporting test trays loaded with semiconductordevices to said testing section.

[0046] In a specific embodiment, in addition to said transport paths fortransporting test trays loaded with semiconductor devices to saidtesting section, two transport paths are provided for transporting testtrays loaded with tested semiconductor devices out of said testingsection after completion of the testing in said testing section.

[0047] By way of example, when the semiconductor device testingapparatus includes a temperature stress applying means for applying atemperature stress of a predetermined temperature to semiconductordevices; said testing section; a heat removing/cold removing means forremoving heat or cold from semiconductor devices having undergone a testin said testing section; a loader section for transferring and reloadingsemiconductor devices onto a test tray; and an unloader section forreceiving and sorting tested semiconductor devices transported from saidtesting section on the basis of the test results, and when saidtemperature stress applying means and said testing section are locatedin the back portion of said semiconductor device testing apparatus whilesaid loader section and said unloader section are located in front ofsaid temperature stress applying means and said testing section, saidheat removing/cold removing means being located in front of said testingsection and underneath said unloader section, two transport paths areprovided in the section of test tray transport path extending from saidtemperature stress applying means to said testing section.

[0048] When said temperature stress applying means, said testingsection, and said heat removing/cold removing means are located in theback portion of said semiconductor device testing apparatus while saidloader section and said unloader section are located in front of saidtemperature stress applying means, said testing section, and said heatremoving/cold removing means, two transport paths are provided in thesection of test tray transport path extending from said temperaturestress applying means via said testing section to heat removing/coldremoving means.

[0049] Said temperature stress applying means is provided with avertical transport mechanism configured to support a plurality of testtrays in the form of a stack with predetermined spacings betweensuccessive trays, and each stage of said vertical transport mechanismfor supporting test trays has a space for accommodating a plurality oftest trays. A plurality of test trays introduced successively from saidloader section are placed on either the uppermost or the lowermost testtray supporting stage of said vertical transport mechanism successivelyfrom the back side toward the front side of said stage with successivetrays either arranged at predetermined small spacings between adjacenttrays or in abutment with each other.

[0050] Said heat removing/cold removing means is provided with avertical transport mechanism configured to support a plurality of testtrays in the form of a stack with predetermined spacings betweensuccessive trays, and each stage of said vertical transport mechanismfor supporting test trays has a space for accommodating a plurality oftest trays such that a plurality of test trays introduced from saidtesting section is placed as such on either the uppermost or thelowermost test tray supporting stage of said vertical transportmechanism.

[0051] According to a second aspect of the present invention, in asemiconductor device testing apparatus of the type including a loadersection for transferring and reloading semiconductor devices onto a testtray, and an unloader section for receiving and sorting testedsemiconductor devices on the basis of the test results, and in whichsemiconductor devices, loaded on a test tray, are transported from saidloader section to a testing section where the semiconductor deviceswhile loaded on the test tray are tested and after completion of thetesting, said tested semiconductor devices loaded on said test tray aretransported from said testing section to said unloader section, followedby being sorted out on the basis of the test results, a semiconductordevice testing apparatus is provided in which a plurality of transportpaths are provided in the section of test tray transport path extendingfrom said unloader section to said loader section.

[0052] According to a third aspect of the present invention, in asemiconductor device testing apparatus of the type in whichsemiconductor devices, loaded on a test tray, are transported to atesting section where the semiconductor devices while loaded on the testtray are tested and after completion of the testing, are carried out ofthe testing section, followed by being sorted out on the basis of thetest results, a semiconductor device testing apparatus is provided inwhich a test tray transport path for transporting test trays loaded withsemiconductor devices to said testing section is a widened path broadenough to transport a plurality of test trays simultaneously with saidplurality of test trays juxtaposed in a direction transverse to saidtest tray transport path.

[0053] In a specific embodiment, in addition to said transport path fortransporting test trays loaded with semiconductor devices to saidtesting section, a transport path for transporting test trays loadedwith tested semiconductor devices out of said testing section aftercompletion of the testing is a widened path broad enough to transport aplurality of test trays simultaneously with said plurality of test traysjuxtaposed in a direction transverse to said test tray transport path.

[0054] For example, when the semiconductor device testing apparatusincludes a temperature stress applying means for applying a temperaturestress of a predetermined temperature to semiconductor devices; saidtesting section; a heat removing/cold removing means for removing heator cold from semiconductor devices having undergone a test in saidtesting section; a loader section for transferring and reloadingsemiconductor devices onto a test tray; and an unloader section forreceiving and sorting tested semiconductor devices transported from saidtesting section on the basis of the test results, and when saidtemperature stress applying means and said testing section are locatedin the back portion of said semiconductor device testing apparatus whilesaid loader section and said unloader section are located in front ofsaid temperature stress applying means and said testing section, saidheat removing/cold removing means being located in front of said testingsection and underneath said unloader section, said widened path broadenough to transport a plurality of test trays simultaneously with saidplurality of test trays juxtaposed in a direction transverse to saidtest tray transport path is provided in the section of test traytransport path extending from said temperature stress applying means tosaid testing section.

[0055] When said temperature stress applying means, said testingsection, and said heat removing/cold removing means are located in theback portion of said semiconductor device testing apparatus while saidloader section and said unloader section are located in front of saidtemperature stress applying means, said testing section, and said heatremoving/cold removing means, said widened path broad enough totransport a plurality of test trays simultaneously with said pluralityof test trays juxtaposed in a direction transverse to said test traytransport path is provided in the section of test tray transport pathextending from said temperature stress applying means via said testingsection to heat removing/cold removing means.

[0056] Said plurality of test trays juxtaposed in a direction transverseto said test tray transport path are in engagement with each other.

[0057] Said temperature stress applying means is provided with avertical transport mechanism configured to support a plurality of testtrays in the form of a stack with predetermined spacings betweensuccessive trays, and each stage of said vertical transport mechanismfor supporting test trays has a space for accommodating a plurality oftwo test trays. A plurality of test trays introduced successively fromsaid loader section are placed on either the uppermost or the lowermosttest tray supporting stage of said vertical transport mechanismsuccessively from the back side toward the front side of said stage withsuccessive trays integrally engaged with each other.

[0058] Said heat removing/cold removing means is provided with avertical transport mechanism configured to support a plurality of testtrays in the form of a stack with predetermined spacings betweensuccessive trays, and each stage of said vertical transport mechanismfor supporting test trays has a space for accommodating a plurality oftest trays. A plurality of test trays in juxtaposition in a directiontransverse to said test tray transport path introduced from said loadersection are placed as such on either the uppermost or the lowermost testtray supporting stage of said vertical transport mechanism.

[0059] According to a fourth aspect of the present invention, in asemiconductor device testing apparatus of the type including a loadersection for transferring and reloading semiconductor devices onto a testtray, and an unloader section for receiving and sorting testedsemiconductor devices on the basis of the test results, and in whichsemiconductor devices, loaded on a test tray, are transported from saidloader section to a testing section where the semiconductor deviceswhile loaded on the test tray are tested and after completion of thetesting, said tested semiconductor devices loaded on said test tray aretransported from said testing section to said unloader section, followedby being sorted out on the basis of the test results, a semiconductordevice testing apparatus is provided in which a widened path broadenough to transport a plurality of test trays simultaneously with saidplurality of test trays juxtaposed in a direction transverse to saidtest tray transport path is provided in the section of test traytransport path extending from said unloader section to said loadersection.

[0060] Said plurality of test trays juxtaposed in a direction transverseto said test tray transport path are in engagement with each other.

[0061] According to a fifth aspect of the present invention, in asemiconductor device testing apparatus of the type in whichsemiconductor devices, loaded on a test tray, are transported to atesting section where the semiconductor devices while loaded on the testtray are tested and after completion of the testing, are carried out ofthe testing section, followed by being sorted out on the basis of thetest results, a semiconductor device testing apparatus is provided inwhich said test tray is generally of a rectangular shape and in which atest tray transport path for transporting test trays loaded withsemiconductor devices to said testing section is a widened path broadenough to transport said rectangular test tray with the major edge ofsaid test tray in front in the direction of travel of the test tray.

[0062] In a specific embodiment, in addition to said transport path fortransporting rectangular test trays loaded with semiconductor devices tosaid testing section, a transport path for transporting a rectangulartest tray loaded with tested semiconductor devices out of said testingsection after completion of the testing in said testing section is awidened path broad enough to transport the rectangular test tray withthe major edge of said test tray in front in the direction of travel ofthe test tray.

[0063] For example, when the semiconductor device testing apparatusincludes a temperature stress applying means for applying a temperaturestress of a predetermined temperature to semiconductor devices; saidtesting section; a heat removing/cold removing means for removing heator cold from semiconductor devices having undergone a test in saidtesting section; a loader section for transferring and reloadingsemiconductor devices onto a test tray; and an unloader section forreceiving and sorting tested semiconductor devices transported from saidtesting section on the basis of the test results, and when saidtemperature stress applying means and said testing section are locatedin the back portion of said semiconductor device testing apparatus whilesaid loader section and said unloader section are located in front ofsaid temperature stress applying means and said testing section, saidheat removing/cold removing means being located in front of said testingsection and underneath said unloader section, said widened path broadenough to transport the rectangular test tray with the major edge ofsaid test tray in front in the direction of travel of the test tray isprovided in the section of test tray transport path extending from saidtemperature stress applying means to said testing section.

[0064] When said temperature stress applying means, said testingsection, and said heat removing/cold removing means are located in theback portion of said semiconductor device testing apparatus while saidloader section and said unloader section are located in front of saidtemperature stress applying means, said testing section, and said heatremoving/cold removing means, said widened path broad enough totransport the rectangular test tray with the major edge of said testtray in front in the direction of travel of the test tray is provided inthe section of test tray transport path extending from said temperaturestress applying means via said testing section to heat removing/coldremoving means.

[0065] In this case, two or a plurality of rectangular test trays aretransported at a time serially with the major edge of each of said testtrays in front in the direction of travel of the test tray along saidtest tray transport path.

[0066] Said temperature stress applying means is provided with avertical transport mechanism configured to support a plurality of testtrays in the form of a stack with predetermined spacings betweensuccessive trays, and each stage of said vertical transport mechanismfor supporting test trays has a space for accommodating a plurality oftest trays in a row with the major edge of each of said test trays infront in the direction of travel of the test tray as said test trays areintroduced from said loader section. A plurality of test traysintroduced successively from said loader section are placed, except thelast introduced test tray, onto either the uppermost or the lowermosttest tray supporting stage of said vertical transport mechanism,followed by being delivered successively in a direction perpendicular tothe direction of introduction while said last introduced test tray isretained as it has been introduced from said loader section, wherebysaid plurality of test trays except said last introduced test tray aredelivered through the outlet of said temperature stress applying meanswith predetermined small spacings between adjacent trays or in abutmentwith each other, and placed on either the uppermost or the lowermosttest tray supporting stage of said vertical transport mechanism injuxtaposition in a row.

[0067] Said heat removing/cold removing means is provided with avertical transport mechanism configured to support a plurality of testtrays in the form of a stack with predetermined spacings betweensuccessive trays, and each stage of said vertical transport mechanismfor supporting test trays has a space for accommodating a plurality oftest trays with the major edge of each of said test trays in front inthe direction of travel of the test tray. A plurality of test traysserially introduced from said loader section are placed as such oneither the uppermost or the lowermost test tray supporting stage of saidvertical transport mechanism.

[0068] According to a sixth aspect of the present invention, in asemiconductor device testing apparatus of the type including a loadersection for transferring and reloading semiconductor devices onto a testtray, and an unloader section for receiving and sorting testedsemiconductor devices on the basis of the test results, and in whichsemiconductor devices, loaded on a test tray, are transported from saidloader section to a testing section where the semiconductor deviceswhile loaded on the test tray are tested and after completion of thetesting, said tested semiconductor devices loaded on said test tray aretransported from said testing section to said unloader section, followedby being sorted out on the basis of the test results, a semiconductordevice testing apparatus is provided in which a widened path broadenough to transport a rectangular test tray with the major edge of saidtest tray in front in the direction of travel of the test tray isprovided in the section of test tray transport path extending from saidunloader section to said loader section.

[0069] In this case as well, two or a plurality of rectangular testtrays are transported at a time serially with the major edge of each ofsaid test trays in front in the direction of travel of the test trayalong said test tray transport path.

[0070] According to a seventh aspect of the present invention, in asemiconductor device testing apparatus of the type in whichsemiconductor devices, loaded on a test tray, are transported to atesting section where the semiconductor devices while loaded on the testtray are tested and after completion of the testing, are carried out ofthe testing section, followed by being sorted out on the basis of thetest results, a semiconductor device testing apparatus is provided inwhich a vertical transport mechanism configured to support a pluralityof test trays in the form of a stack with predetermined spacings betweensuccessive trays is provided in a constant temperature chambercontaining a temperature stress applying means for applying atemperature stress of a predetermined temperature to semiconductordevices and said testing section, each stage of said vertical transportmechanism for supporting test trays having a space for accommodating aplurality of test trays so that a plurality of test trays may besimultaneously transported to said testing section.

[0071] Said semiconductor device testing apparatus further includes aloader section for transferring and reloading semiconductor devices ontoa test tray and an unloader section for receiving and sorting testedsemiconductor devices on the basis of the test results, and each of saidloader section and unloader section is provided with a verticaltransport mechanism configured to support a plurality of test trays inthe form of a stack with predetermined spacings between successivetrays, each stage of said vertical transport mechanism for supportingtest trays having a space for accommodating one test tray.

[0072] In an alternative embodiment, said semiconductor device testingapparatus further includes a loader section for transferring andreloading semiconductor devices onto a test tray and an unloader sectionfor receiving and sorting tested semiconductor devices on the basis ofthe test results, and each of said loader section and unloader sectionis provided with a vertical transport mechanism configured to support aplurality of test trays in the form of a stack with predeterminedspacings between successive trays, each stage of said vertical transportmechanism for supporting test trays having a space for accommodating aplurality of test trays.

[0073] In a specific embodiment, a tester head is mounted on the top ofsaid constant temperature chamber, and when a plurality of test traysplaced on each test tray supporting stage are raised up to the uppermosttest tray supporting stage by said vertical transport mechanism in saidconstant temperature chamber, a predetermined number of semiconductordevices out of the semiconductor devices loaded on said plurality oftest trays on the uppermost test tray supporting stage are electricallyconnectable with a device socket mounted on said tester head, with saiddevice socket facing downwardly.

[0074] Each of said stages for supporting test tray of said verticaltransport mechanism in said constant temperature chamber has a space foraccommodating a plurality of test trays in a row as said test tray traysare introduced from said loader section. Said plurality of test traysintroduced successively from said loader section are placed, except thelast introduced test tray, onto either the uppermost or the lowermosttest tray supporting stage of said vertical transport mechanism,followed by being delivered successively in a direction perpendicular tothe direction of introduction while said last introduced test tray isretained as it has been introduced from said loader section.

[0075] According to a eighth aspect of the present invention, test traysuseful with said semiconductor device testing apparatus provided in theaforesaid third and fourth aspects of the invention are provided, eachof said test trays comprising a rectangular frame having one of twoopposite edges formed with recess means and the other of the oppositeedges formed with protrusion means, said test trays being integrallyjoinable with each other by said protrusion means of one of said testtrays being engaged with said recess means of an other one of said testtrays.

[0076] According to a ninth aspect of the present invention, test traysuseful with said semiconductor device testing apparatus provided in theaforesaid third and fourth aspects of the invention are provided, eachof said test trays comprising a rectangular frame having one of twoopposite edges provided with pivotable engagement protrusion means andthe other of the opposite edges provided with recess means, said testtrays being integrally joinable with each other by said engagementprotrusion means of one of said test trays being engaged with saidrecess means of an other one of said test trays.

[0077] According to a tenth aspect of the present invention, asemiconductor device testing apparatus is provided in which a plate-likemember is used, said plate-like member having a pair of openings formedin juxtaposition at a predetermined spacing therebetween foraccommodating two test trays, one fitted in each of said openings, sothat the two test trays in unison with said plate-like member may betransported along said test tray transport path.

BRIEF DESCRIPTION OF THE DRAWINGS

[0078]FIG. 1 is a plan view illustrating the general construction of afirst embodiment of the semiconductor device testing apparatus accordingto the present invention;

[0079]FIG. 2 is a plan view illustrating the general construction of asecond embodiment of the semiconductor device testing apparatusaccording to the present invention;

[0080] FIGS. 3(a) and 3(b) are representations illustrating thefunctional advantages of the semiconductor device testing apparatus ofthe second embodiment shown in FIG. 2;

[0081]FIG. 4 is a plan view illustrating the general construction of athird embodiment of the semiconductor device testing apparatus accordingto the present invention;

[0082]FIG. 5 is a plan view illustrating the engagement means forengaging two test trays with each other to integrally join themtogether;

[0083]FIG. 6 is a representation illustrating one example of guidemembers of a transport for transporting two test trays in integrallyjoined state, FIG. 6A being a plan view and FIG. 6B being a side view asseen from the left side of FIG. 6 A;

[0084]FIG. 7 is a representation illustrating another example of theengagement means for engaging two test trays with each other tointegrally join them, FIG. 7A being a plan view, FIGS. 7B, 7C and 7Dbeing perspective views, respectively and FIG. 7E being across-sectional view of FIG. 7D taken along the line 7E-7E;

[0085]FIG. 8 is a perspective view illustrating the general constructionof a fifth embodiment of the semiconductor device testing apparatusaccording to the present invention;

[0086]FIG. 9 is a plan view, partly in a perspective view, illustratingthe general construction of a sixth embodiment of the semiconductordevice testing apparatus according to the present invention;

[0087]FIG. 10 is a front view of the semiconductor device testingapparatus of the sixth embodiment shown in FIG. 9 with the constanttemperature chamber section shown in a cross-sectional view;

[0088]FIG. 11 is a plan view illustrating the general construction ofone example of the conventional semiconductor device testing apparatus;

[0089]FIG. 12 is an exploded perspective view illustrating theconstruction of an example of the test tray for use with thesemiconductor device testing apparatus;

[0090]FIG. 13 is an enlarged cross-sectional view illustrating themanner in which the IC under test stored in the test tray shown in FIG.11 is in electrical connection with the tester head;

[0091]FIG. 14 is a plan view illustrating the order in which the ICsstored in a test tray are subjected to testing; and

[0092]FIG. 15 is a perspective view illustrating the construction of anIC storage rack for use with the semiconductor device testing apparatusshown in FIG. 11.

BEST MODES FOR CARRYING OUT THE INVENTION

[0093]FIG. 1 shows the general construction of the semiconductor devicetesting apparatus of a first embodiment according to the presentinvention. Since as in the foregoing description of the prior artexample the present invention in the first embodiment as well as in theother embodiments is described with reference to ICs which are typicalof semiconductor devices, the semiconductor device testing apparatuswill be simply referred to as IC tester hereinafter. Further, theelements shown in FIG. 1 corresponding to those of FIG. 11 aredesignated by the same reference numerals and will not be discussedagain in details, unless required.

[0094] Like the IC tester shown in FIG. 11, the IC tester of the presentinvention as illustrated in FIG. 1 is configured such that a constanttemperature chamber 4 including a soak chamber 41 and a testing section42, and an exit chamber 5 are arranged in the left to right direction asviewed in the drawing (referred to as X-axis direction herein) in therear portion of the IC tester while in front of the constant temperaturechamber 4 and the exit chamber 5 there are located a loader section 7and an unloader section 8. The loader section 7 is adapted fortransferring and reloading ICs under test onto test trays 3 capable ofwithstanding high/low temperatures while the unloader section 8 isadapted for transferring and reloading tested ICs which have beencarried on the test tray 3 out through the exit chamber 5 subsequentlyto being tested in the testing section 42 of the constant temperaturechamber 4 from the test tray 3 to the universal tray. Further, in theforefront of the IC tester there is located a storage section 11 forstoring universal trays 1 loaded with ICs to be tested and universaltrays 1 loaded with ICs already tested and sorted.

[0095] More specifically, the soak chamber 41, the testing section 42,and the exit chamber 5 are arranged in the order named from left toright in the X-axis direction in the drawing, and the loader section 7and the unloader section 8 are located in front of the soak chamber 41of the constant temperature chamber 4 and in front of the exit chamber5, respectively. Accordingly, as in the conventional IC tester, the testtray 3 is delivered into the constant temperature chamber 4 in thedirection (upward-downward direction as viewed in the drawing which isreferred to as Y-axis direction herein) which is perpendicular to thedirection (X-axis direction) in which it has been conveyed from theunloader section 8 to the loader section 7. From the constanttemperature chamber 4, the test tray 3 is again delivered out in thedirection which is perpendicular to the direction in which it has beenintroduced from the loader section 7. Likewise, from the exit chamber 5,the test tray 3 is delivered out in the direction which is perpendicularto the direction in which it has been introduced from the constanttemperature chamber 4. From the unloader section 8, the test tray 3 isagain discharged in the direction which is perpendicular to thedirection in which it has been introduced from the exit chamber 5. Inother words, when the test tray 3 is transported from the unloadersection 8 to the loader section 7, one of the minor edges of the traytakes the lead in the movement; during the transport from the loadersection 7 to the constant temperature chamber 4 the test tray 3 isadvanced with one of its major edge in the front; in transit from theconstant temperature chamber 4 to the exit chamber 5 the test tray 3 ismoved with the other of its minor edges; and then the test tray 3 istransported from the exit chamber 5 to the unloader section 8 with theother of its major edges in the front.

[0096] The soak chamber 41 of the constant temperature chamber 4 isdesigned for applying temperature stresses of either a predeterminedhigh or low temperature on ICs under test loaded on a test tray 3 in theloader section 7 while the testing section 42 of the constanttemperature chamber 4 is designed for executing electrical tests on theICs under the predetermined temperature stress imposed in the soakchamber 41. In order to maintain the ICs loaded with temperaturestresses of either a predetermined high or low temperature in thattemperature during the test, the soak chamber 41 and testing section 42are both contained in the constant temperature chamber 4 capable ofmaintaining the interior atmosphere at a predetermined temperature.

[0097] The exit chamber 5 is designed for relieving tested ICs of heator cold to restore them to the outside temperature (room temperature).That is, the exit chamber 5 cools the ICs with forced air down to theroom temperature if the ICs under test were loaded with a hightemperature stress on the order of 120° C., for example in the soakchamber 41. If the ICs under test had a low temperature on the order of−30° C. applied thereto in the soak chamber 41, the exit chamber 5 heatsthem with heated air or a heater back to a temperature at which nocondensation occurs.

[0098] The unloader section 8 is configured to sort tested ICs placed ona test tray by categories on the basis of the data of the test resultsand load them on the corresponding universal trays. In this example, theunloader section 8 is configured to provide for stopping test trays 3 attwo positions A and B The ICs on the test trays 3 stopped at the firstposition A and the second position B are sorted out based on the data ofthe test results and transferred onto and stored in the universal traysof the corresponding categories at rest at the universal tray setpositions 2, four universal trays 1 a, 1 b, 1 c and 1 d in the exampleillustrated.

[0099] The test tray 3 may be of the same size and construction as thatused with the conventional IC tester already described with reference toFIG. 11. That is, the test tray 3 has the construction as shown in FIG.12. The test tray 3 is moved in a circulating manner from and back tothe loader section 7 sequentially through the soak chamber 41 and thetesting section 42 in the constant temperature chamber 4, the exitchamber 5, and the unloader section 8. In this path of circulatingtravel, there are disposed a predetermined number of test trays 3 whichare successively moved in the directions as indicated by thickcross-hatched arrows in FIG. 1 by a test tray transport.

[0100] In this first embodiment of the invention, as will be appreciatedfrom FIG. 1, the depth (length in the Y-axis direction) of the constanttemperature chamber 4 and the exit chamber 5 is expanded as compared tothe prior art IC tester by a dimension corresponding approximately toone transverse width (length of the minor edge) of the rectangular testtray 3, and there are provided two generally parallel paths of transportfor test trays 3 extending successively through the soak chamber 41 andthe testing section 42 in the constant temperature chamber 4 and thenthrough the exit chamber 5 so that two test trays 3 as shown may besimultaneously transported along the two paths of transport. In thiscase, the total width (length in the Y-axis direction) of the two pathsof transport is approximately equal to the sum of transverse widths oftwo test trays, so that provision of two paths of transport increasesthe depth (length in the Y-axis direction) of the IC tester only by adimension corresponding approximately to the length of the minor edge ofthe test tray 3.

[0101] The operation of the IC tester constructed as described justabove will now be explained.

[0102] A test tray 3 having ICs under test loaded thereon from auniversal tray 1 in the loader section 7 is conveyed with one of itsmajor edges in the front from the loader section 7 to the constanttemperature chamber 4 and is introduced into the soak chamber 41 throughan inlet formed in the front side of the constant temperature chamber 4The soak chamber 41 is equipped therein with a vertical transportmechanism adapted to support a plurality of (say, five) test trays 3stacked one on another with predetermined spacings therebetween.

[0103] In this embodiment, each stage of the vertical transportmechanism for supporting a test tray thereon has a depth (correspondingto the dimension of the outlet of the soak chamber 41) approximatelyequal to the sum of transverse widths of two test trays and an inletsized to be approximately equal to one length of the major edge of thetest tray (corresponding to the dimension of the inlet of the soakchamber 41 as measured in the X-axis direction). The first test tray 3received from the loader section 7 is placed on the uppermost stage ofthe vertical transport mechanism in the back half section (the upperhalf section as viewed in the Y-axis direction) of the stage andsupported by supporting members associated with that stage.

[0104] The vertical transport mechanism is stopped in operation untiltwo test trays are transported onto the uppermost stage. Once the secondtest tray 3 has been transported from the loader section 7 onto theuppermost stage of the vertical transport mechanism and accommodated inthe front half section (the lower half section as viewed in the Y-axisdirection) of the stage either at a predetermined spacing from or inabutment with the first test tray, the vertical transport mechanism isactuated to move the test trays on the successive stages downwardly byone stage in the vertical direction (which is referred to Z-axisdirection). Alternatively, the arrangement may be such that after thefirst test tray has been placed into the back half section on theuppermost stage of the vertical transport mechanism, the operation ofthe vertical transport mechanism is stopped until the lapse of apredetermined period of time during which the downward movement of thetest trays on the successive stages is ceased.

[0105] The vertical transport mechanism is configured to support twotest trays on each stage and is operative to move the two test trays oneach stage down successively to the next lower stage.

[0106] While two test trays on the uppermost stage are moved downthrough the successive stages to the lowermost stage, and during awaiting time until the testing section 42 is vacated (available for nexttesting), the ICs to be tested on the two test trays are loaded with atemperature stress of either a predetermined high or low temperature.

[0107] Once the two test trays have been moved down to the lowermoststage, they are almost simultaneously delivered out along the respectivepaths of transport through the outlet of the soak chamber 41 into thetesting section 42 which on the left-hand side in the X-axis direction,adjoins and communicates with the lower portion of the soak chamber 41.It is thus will be appreciated that the two test trays are delivered outof the soak chamber 41 in a direction perpendicular to the direction ofintroduction thereinto. The path along which the first test tray istransported from the soak chamber 41 through the testing section 42 tothe exit chamber 5 is referred to as the first path of transport whilethe path along which the second test tray is transported from the soakchamber 41 through the testing section 42 to the exit chamber 5 isreferred to as the second path of transport.

[0108] The testing section 42 is equipped with a single tester head (notshown) disposed at the corresponding position below the two paths oftransport for test trays. Two test trays almost simultaneously deliveredout of the soak chamber 41 are transported along the first and secondseparate paths of transport to the testing section 42 and are halted atpredetermined positions overlying the corresponding device sockets (notshown) mounted on the tester head. Subsequently, a predetermined numberof ICs under test out of those loaded on the test trays are brought intoelectrical contact with the corresponding device sockets mounted on thetester head while the ICs are placed on the test trays.

[0109] Upon completion of testing on all of the ICs on the two testtrays through the tester heads, those two test trays are transportedalong the respective paths of transport from the testing section 42 tothe exit chamber 5 where the tested ICs are relieved of heat or cold.

[0110] It is to be noted that instead of providing a single tester head,there may be two tester heads, one for each of the two test traytransport paths which have mounted thereon device sockets adapted tocontact with the ICs on the two test trays corresponding to the twotester heads. It should also be noted that while two test trays aretransported from the soak chamber 41 to the testing section 42, and thenfrom the testing section 42 to the exit chamber 5, two test trays neednot necessarily be simultaneously transported.

[0111] Like the soak chamber 41, the exit chamber 5 is also equippedwith a vertical transport mechanism adapted to support a plurality of(say, five) test trays 3 stacked one on another with predeterminedspacings therebetween.

[0112] In this embodiment, each stage of the vertical transportmechanism for supporting a test tray thereon in the exit chamber 5 hasan inlet sized to be approximately equal to the sum of transverse widthsof two test trays and approximately equal to one length of the majoredge of the test tray (corresponding to the dimension of the inlet ofthe exit chamber 5 as measured in the Y-axis direction) and a depthapproximately equal to one length of the major edge of the test tray(corresponding to the dimension of the outlet of the exit chamber 5 asmeasured in the X-axis direction). The first test tray 3 introducedalong the first path of transport from the testing section 42 is placedon the lowermost stage of the vertical transport mechanism in the backhalf section of that stage while the second test tray 3 introduced alongthe second path of transport from the testing section 42 is placed onthe lowermost stage of the vertical transport mechanism in the fronthalf section of that stage, and the two test trays are supported bysupporting members associated with that stage.

[0113] The vertical transport mechanism is at rest in operation untiltwo test trays are transported onto the lowermost stage. Once two testtrays has been transported from the testing section 42 onto thelowermost stage of the vertical transport mechanism, the verticaltransport mechanism is actuated to move the test trays on the successivestages upwardly by one stage in the vertical direction. While two testtrays on the lowermost stage are moved up to the uppermost stage by theupward movement of the successive stages by actuation of the verticaltransport mechanism, the tested ICs are relieved of either heat or coldto be restored to the outside temperature (room temperature).

[0114] As already noted, since the IC test is conducted on ICs having adesired temperature stress in a wide range of temperatures such as from−55° C. to +125° C. imposed thereon in the soak chamber 41, the exitchamber 5 cools the ICs with forced air down to the room temperature ifthe ICs have had a high temperature of, say, about 120° C. appliedthereto in the soak chamber 41. If ICs have had a low temperature of,say, about −30° C. applied thereto in the soak chamber 41, the exitchamber 5 heats them with heated air or a heater up to a temperature atwhich no condensation occurs.

[0115] After the heat removal or cold removal process, the second testtray 3 placed on the front half section of the uppermost stage of thevertical transport mechanism is conveyed from the exit chamber 5 to theposition A at the unloader section 8 through the outlet of the exitchamber extending in the direction (facing on the front of the exitchamber 5) perpendicular to that in which it has been introduced fromthe testing section 42 into the exit chamber 5. Disposed closest to thefirst position A are universal trays 1 a and 1 b. Assuming thatclassification categories 1 and 2 are allotted to these universal trays1 a and 1 b, respectively, while the test tray 3 is stopped at the firstposition A, only the tested ICs belonging to the categories 1 and 2 arepicked up from the test tray 3 held at the first position A, andtransferred onto the corresponding universal trays 1 a and 1 b,respectively. Once the test tray 3 at rest at the first position A hasbeen depleted of the ICs belonging to the categories 1 and 2, the testtray is moved to the second position B.

[0116] Arranged closest to the second position B are universal trays 1 cand 1 d. Assuming that classification categories 3 and 4 are allotted tothese universal trays 1 c and 1 d, respectively, the tested ICsbelonging to the categories 3 and 4 are picked up from the test tray 3held at the second position B and transferred onto the correspondinguniversal trays 1 c and 1 d, respectively.

[0117] Next, the first test tray 3 placed on the back half section ofthe uppermost stage of the vertical transport mechanism is conveyed fromthe exit chamber 5 through the outlet thereof to the position A at theunloader section 8 and is halted at that position. The conveyance of thefirst test tray to the unloader section 8 takes place eitherconcurrently with or after the conveyance of the second test tray fromthe position A to the position of the unloader section 8.

[0118] It will be appreciated that the distance for the X-Y transport 81required to travel for the sorting operation can be reduced by thearrangement described above in which the X-Y transport 81 is shared bythe two unloader sections (represented by the first and second positionsA and B) and in which the sorting operations are limited to theuniversal trays 1 a, 1 b and universal trays 1 c, 1 d closest to thetest tray stop positions A and B, respectively. Consequently, thisconstruction permits the overall processing time required for thesorting to be shortened, despite the fact that the single X-Y transport81 is used for the sorting operation.

[0119] In this embodiment as well, it is noted that the number ofuniversal trays 1 that can be installed at the universal tray setpositions 12 in the unloader section 8 is limited to four by the spaceavailable. Hence, the number of categories into which ICs can be sortedin real time operation is limited to four categories 1 to 4 as notedabove. While four categories would generally be sufficient to coverthree categories for subclassifying “conforming articles” into high,medium and low response speed elements in addition to one categoryallotted to “non-conforming article,” in some instances there may besome among the tested ICs which do not belong to any of thesecategories. Should there be found any tested ICs which should beclassified into a category other than the four categories, a universaltray 1 assigned to the additional category should be taken from theempty tray storage rack 1E (the lower right corner area in FIG. 1) ofthe IC storage section 11 and be transported into the unloader section 8to store the ICs of the additional category. When this is to be done, itis also needed to transport any one of the universal trays positioned inthe unloader section 8 to the IC storage section 11 for storage therein.

[0120] If the replacement of the universal trays is effected in thecourse of the sorting operation, the latter operation would have to beinterrupted during the replacement. For this reason, this embodimentalso disposes a buffer section 6 between the stop positions A and B forthe test tray 3 and the locations of the universal trays 1 a-1 d fortemporarily keeping the tested ICs belonging to a category of rareoccurrence.

[0121] The buffer section 6 may have a capacity of accommodating, sayabout twenty to thirty ICs and be equipped with a memory portion forstoring the category and locations of ICs placed in the individual ICpockets of the buffer section 6. With this arrangement, between thesorting operations or upon the buffer section 6 being filled with ICs, auniversal tray for the category to which the ICs kept in the buffersection belong is carried from the IC storage section 11 to theuniversal tray set position 12 at the unloader section 8 to store theICs in that universal tray. It should be noted that ICs temporarily keptin the buffer section 6 may be scattered over a plurality of categories.In that case, it would be required to transport as many universal traysas the number of categories at a time from the IC storage section 11 tothe unloader section 8.

[0122] The test tray 3 emptied in the unloader section 8 is deliveredback to the loader section/where it is again loaded with ICs beingtested from the universal tray 1 to repeat the same steps of operation.

[0123] The IC transport 71 for transferring ICs from the universal tray1 to the test tray 3 in the loader section 7 may be of the sameconstruction as that used with the conventional IC tester alreadydescribed, and may comprise a pair of opposed parallel rails 71A, 71Bmounted over the loader section 7 at the ends thereof opposed in theX-axis direction and extending in the Y-axis direction, a movable arm71C spanning and mounted at opposite ends on the pair of rails 71A, 71Bfor movement in the Y-axis direction, and a movable head, not shown(which is known in the art concerned as pick-and-place head) carried onthe movable arm 71C for movement therealong longitudinally of the arm,that is, in the X-axis direction.

[0124] The movable head has an IC pick-up pad (IC grasping member)vertically movably mounted on its bottom surface. The movement of themovable head in the X-Y-axis directions and the downward movement of thepick-up pad bring the pick-up pad into abutment with the ICs placed onthe universal tray 1 at rest at the universal tray set position 12 toattract and grasp them by vacuum suction, for instance for transfer fromthe universal tray 1 to the test tray 3. The movable head may beprovided with a plurality of, say, eight pick-up pads so that eight ICsat a time may be transported from the universal tray 1 to the test tray3.

[0125] Further, a position corrector 2 for correcting the orientation orposition of an IC called “preciser” is located between the universaltray set position 12 and the stop position for the test tray 3. Theoperation of this IC position corrector 2 has already been describedhereinabove, and further description is omitted.

[0126] The unloader section 8 is also equipped with an X-Y transport 81which is identical in construction to the X-Y transport 71 provided forthe loader section 7. The X-Y transport 81 is mounted spanning the firstposition A and the second position B and performs to transship thetested ICs from the test tray 3 delivered out to the positions A and Bin the unloader section 8 onto the corresponding universal tray 1.

[0127] The X-Y transport 81 comprises a pair of spaced parallel rails81A, 81B mounted over the unloader section 8 at the ends thereof opposedin the X-axis direction and extending in the Y-axis direction, a movablearm 81C spanning and mounted at opposite ends on the pair of rails 81A,81B for movement in the Y-axis direction, and a movable head, not shown(which is known in the art concerned as pick-and-place head) carried onthe movable arm 71C for movement therealong longitudinally of the arm,that is, in the X-axis direction.

[0128] As in the illustrated prior art IC tester, a tray transport,although not shown in FIG. 1, is disposed above the IC-to-be-testedstorage racks and the tested-IC storage racks for movement over theentire extent of those storage racks in the direction of arrangement ofthe racks (in the X-axis direction). There have already been describedhereinabove the various operations of this tray transport including theoperation of holding a universal tray 1 loaded with ICs under test atthe universal tray set position in the loader section 7, the operationof holding four empty universal trays 1 a-1 d at the respectiveuniversal tray set positions 12 in the unloader section 8, the operationof storing a fully filled universal tray in the corresponding traystorage position, and the operation of, in the event that there may befound any tested IC which does not belong to any of the categoriesallotted to the designated universal trays held at the set positions 12,transporting to the set position in the unloader section 8 a universaltray for storing such IC of an other al category. Therefore, suchdescription is not repeated here.

[0129] With the construction described just above, while there is onlyone path of transport for the test tray running from the exit chamber 5through the unloader section 8 to the soak chamber 41 as in theillustrated prior art IC tester, two such paths are provided from thesoak chamber 41 through the testing section 42 to the exit chamber 5. Itis thus to be appreciated that this permits ICs under test placed on twotest trays to be simultaneously tested in the testing section 42 inspite of the use of the conventionally used test tray as such, resultingin doubling the simultaneous measurement throughput in number of ICs.Consequently, in the case that a relatively long time is required pertest in the testing section 42, the doubled simultaneous measurementthroughput in number reduces the time required to complete the testingon all of the ICs to nearly half, producing the advantage of greatlysaving the testing cost per IC.

[0130] It is noted here that the provision of two paths of test traytransport running from the soak chamber 41 through the testing section42 to the exit chamber 5 as in the embodiment described abovenecessitates one independent drive means for each of the transportpaths. However, in the case of relatively long time required per test inthe testing section 42, the test tray transport mechanism need not be sofast in operation, permitting the use of relatively inexpensive testtray transport mechanisms so that the increase in the cost involved inproviding two test tray transport mechanisms may be only marginal. Itwill thus be appreciated that the merit of reducing the testing cost perIC is much greater.

[0131] In addition, in the construction according to the firstembodiment described above, the overall size of the IC tester need beenlarged only in depth by only about one length of the minor edge of thetest tray. Consequently, the advantages are obtained that the depthdimension of the entire IC tester may be made considerably smaller andthat the apparatus may be manufactured less expensively, as compared tothe construction which would result if in the prior art IC tester shownin FIG. 11 two of the construction comprising the soak chamber 41, thetesting section 42 and the exit chamber 5 were provided in order toestablish two paths of test tray transport extending from the soakchamber 41 through the testing section 42 to the exit chamber 5.

[0132] As is well known in the art, the number of ICs which can besimultaneously tested in the testing section 42 depends on the number ofIC sockets which can be mounted on a tester head. Tester heads areconstructed separately from the IC tester proper (which is called mainframe in the art concerned) and are mounted in the testing section ofthe handler. It should be noted in this regard that the IC tester isusually configured to permit withdrawal of tester heads rearwardly ofthe handler, in consideration of the considerable weight of the testerhead as well as the fact that tester heads are exchanged in accordancewith the type of ICs to be tested, the contents of the test, the size oftest trays used, and others.

[0133] As will be appreciated, enlarging the size of a tester head in anattempt to increase the number of IC sockets which can be mounted on thetester head would require an enlarged space available for mounting thelarge-sized tester head, resulting in oversizing the handler, whichwould ultimately lead to a considerable enlargement of the IC tester asa whole, taking into account also the space needed to facilitate thewithdrawal of the tester head rearwardly of the handler. In addition,the increased weight of the tester head will also cause the problem of asingle operator being unable to carry out the operation of exchangingthe tester heads. In view of this, it is preferable that the size of thetester head be as small as possible, and its size is generally specifieddepending on the size of test trays used.

[0134] In this regard, mounted on the top of the tester head is aperformance board on which IC sockets are mounted. Since the size offixture (which is called Hi-fix in the art concerned) for mounting thetester head in the testing section 42 of the constant temperaturechamber 4 is determined depending on the size of the tester head, thereis a limit to the number of IC sockets which can be mounted on theperformance board which is electrically connected through thisperformance board with the measuring circuit (including drivers,comparators and others) contained in the interior of the tester head.For instance, when the test tray 3 as shown in FIG. 12 is sized toaccommodate sixty-four ICs, it is possible to mount up to thirty-two ICsockets on the performance board. Accordingly, in the case that theloading capacity of the test tray is sixty-four pieces, it is a practiceto test the ICs in two lots, each lot comprising thirty-two (half thetotal number) ICs for simultaneous testing, since the number of IC whichcan be tested simultaneously (simultaneous measurement throughput innumber) is thirty-two at maximum. It is thus impossible tosimultaneously test all of sixty-four ICs on the test tray 3 in thetesting section 42. It is noted that in some instance sixteen IC socketsmay be mounted on the tester head as noted with reference to FIG. 14.

[0135] If the number of ICs which can be loaded on a test tray isincreased by enlarging the test tray by increasing the Y-axis and/orX-axis dimensions, it would be possible to correspondingly increase thesize of the tester head whereby the number of IC sockets may be mountedon the tester head (performance board) could be augmented, leading to anincrease in the number of ICs which can be simultaneously tested in thetesting section 42. Eventually, the IC testing time required in thetesting section 42 could be reduced.

[0136] However, simply enlarging the external size of the test tray 3 isnot preferable since it would exert various effects on the various partsof the entire IC tester.

[0137] The reasons for this are as follows: As shown in FIGS. 1 and 11,the constant temperature chamber 4 contains the soak chamber 41 and thetesting section 42 adjoining the former on the right side thereof asviewed in the X-axis direction, and adjoining the testing section 42 onthe right side thereof in the X-axis direction is the exit chamber 5.Further, the loader section 7 and unloader section 8 are disposed infront of the constant temperature chamber 4 and the exit chamber 5,respectively and adjoin them in the Y-axis direction.

[0138] These soak chamber 41, testing section 42, testing section 42,loader section 7 and unloader section 8 are all indispensable componentsfor the IC tester, and none of them can be eliminated.

[0139] Assuming here that the loading capacity of the test tray wasdoubled by simply doubling the external size of the test tray 3 in theY-axis dimension while retaining the external size in the X-axisdimension as such, the surface area of the test tray 3 would beincreased by two, necessitating the region required of the soak chamber41 and testing section 42 in the constant temperature chamber 4 to bedoubled. With regard to the loader section 7 and unloader section 8 aswell, about two-fold region would likewise be required for at least thepath of transport for the test tray. Consequently, if the external sizeof the test tray 3 in the Y-axis dimension was doubled with an attendanttwo-fold increase in the surface area of the test tray 3, the Y-axis(forward-rearward direction) dimension of the IC tester summing up theconstant temperature chamber 4 (or the exit chamber 5) and the loadersection 7 (or the unloader section 8) would be increased by about two,since 2+2=4 in the prior art example.

[0140] However, in the case that two paths of test tray transportextending from the soak chamber 41 through the testing section 42 to theexit chamber 5 are provided as in the first embodiment described above,the regions required of the soak chamber 41, the testing section 42 andthe exit chamber 5, respectively are doubled, but since the regionsrequired of the loader section 7 and unloader section 8 remain the samein size (one-fold) as in the illustrated prior art IC tester, the Y-axis(forward-rearward direction) dimension of the IC tester summing up theconstant temperature chamber 4 (or the exit chamber 5) and the loadersection 7 (or the unloader section 8) will be increased by only one anda half as 2+1=3.

[0141] As discussed above, in contrast to the case where the surfacearea or loading capacity of the test tray is doubled, the firstembodiment according to the present invention provides the advantagethat the region required of the IC tester need only have the Y-axis(forward-rearward direction) dimension of the IC tester summing up theconstant temperature chamber 4 (or the exit chamber 5) and the loadersection 7 (or the unloader section 8) solely increased by about one anda half in spite of the fact that the number of ICs which can besimultaneously tested in the testing section 42 has been doubled.Namely, because of the presence of the storage section 11 for storinguniversal trays, the increase in the surface area of the IC tester(handler) in terms of the Y-axis direction is less than a factor of 1.5,so that the size of the IC tester as a whole is not so large.

[0142] Further, as noted above, the test tray 3 comprises a rectangularframe 30 and a multiplicity of IC carriers 34 for accommodating ICs,supported by the frame 30, and all of these parts are made of theaforementioned material capable of withstanding test measurements undera wide range of temperatures from −55° C. to +125° C. An aggregate ofsixty-four IC carriers 34 has a considerably heavy weight. The frame 30supporting IC carriers is also of a considerably weight since it need beof construction sturdy enough to support such considerably heavy ICcarriers 34. Consequently, the sum of the weight of sixty-four ICcarriers 34 on the test tray and the weight of the frame 30 is sosignificant. On top of that, doubling the external size of the test tray3 in the Y-axis dimension would also increase the weight thereof byabout two.

[0143] In this regard, when test trays are initially loaded in thehandler or replaced, a single operator usually carries a plurality oftest trays stacked one on another, but an increase in the weight of thetest tray as mentioned above would make it difficult for a singleoperator to handle such test trays.

[0144] In addition, since the frame 30 and cleats 31 of the test tray 3are constructed of aluminum alloy and exposed to a wide range oftemperatures ranging over 180° C. from −55° C. to +125° C., the externalsize of the test tray is highly influenced by thermalexpansion/contraction. Doubling the external size of the test tray 3 inthe Y-axis dimension would naturally result in increasing the thermalexpansion/contraction by a factor of two. Such increased thermalexpansion/contraction of the test tray 3 is very likely to reduce theaccuracy of electrical contact between ICs placed on the test tray andthe IC socket mounted on the performance board of the tester head.

[0145] However, the first embodiment according to the present inventiondescribed above permits the use of the conventional test tray as such,because two of the path of test tray transport are provided only forthat portion of the path extending from the soak chamber 41 through thetesting section 42 to the exit chamber 5 whereas the path of test traytransport extending from the exit chamber 5 through the unloader section8 to the soak chamber 41 remains single as in the illustrated prior artIC tester. Accordingly, the first embodiment is not distinguished at allfrom the prior art IC tester with respect to the weight and thermalexpansion/contraction of the test tray.

[0146] It should be noted here that in the case that the time requiredper test in the testing section 42 is short, there is little need forenhancing the simultaneous measurement throughput in number of ICs as isthe case with the first embodiment, but that it is of more importance tofurther increase the number of ICs that can be handled per unit time bythe transporting and handling mechanism including the X-Y transports 71and 81 for the loader section 7 and the unloader section 8, respectively(reduce the time required for handling ICs). However, increasing thenumber of ICs handled per unit time involves a fairly high cost, and itis difficult to increase the number of ICs handled beyond a certainlimit.

[0147] In view of this, it is preferable that the configurationaccording to the second embodiment of the present invention asillustrated in FIG. 2 be employed in the case of relatively short timerequired per test in the testing section 42. As will be appreciated fromFIG. 2, in the second embodiment, although the path of test traytransport is single for that portion of the path extending from the soakchamber 41 through the testing section 42 to the exit chamber 5 as inthe illustrated prior art IC tester, the depth (length in the Y-axisdirection) of the loader section 7 and the unloader section 8 isexpanded by a dimension corresponding approximately to one transversewidth (length of the minor edge) of the rectangular test tray 3, and twogenerally parallel paths of transport for test trays 3 are provided forthe section of the transport path extending from the unloader section 8to the loader section 7 so that two test trays 3 as shown may besimultaneously transported along these two paths of transport.

[0148] Accordingly, in this second embodiment as well, the total width(length in the Y-axis direction) of the two paths of transport isapproximately equal to the sum of transverse widths of two test trays,so that provision of two paths of transport increases the depth (lengthin the Y-axis direction) of the IC tester only by a dimensioncorresponding approximately to the length of the minor edge of the testtray 3.

[0149] In order to further increase the number of ICs that can behandled by the transporting and handling mechanism including the X-Ytransports 71 and 81 for the loader section 7 and the unloader section8, respectively, it would be ideal, to use a transporting and handlingmechanism, for example capable of placing sixty-four ICs to be testedfrom a universal tray into all of the sixty-four IC carriers 34 of atest tray 3 in one operation in the loader section 7 and picking up(grasping) all of sixty-four tested ICs from the test tray 3 in oneoperation in the unloader section 8. However, such transporting andhandling mechanism is not currently in practical use.

[0150] However, although it is impossible to grasp all of sixty-four ICsto be tested or already tested (corresponding in number to the loadingcapacity of one test tray) at a time, it is possible to have thetransporting and handling mechanism including the X-Y transports 71 and81 grasp more than eight, say ten, or twelve ICs to be tested or alreadytested all at a time. To this end, it is required that there be as manyICs to be tested or already tested as possible present in the loadersection 7 and the unloader section 8, respectively. The reason is thatif the number of ICs to be tested or already tested present in theloader section 7 and the unloader section 8, respectively is greater ascompared to the number of ICs that can be handled by the X-Y transports71 and 81 (the number of pick-up pads of the movable head(pick-and-place head)), there would be less probability that some of thepick-up pads of the movable heads of these X-Y transports might be movedin an empty state (grasping no ICs), ensuring more efficienttransportation of ICs, even if the number of ICs that can besimultaneously handled by the X-Y transports 71 and 81.

[0151] This is the reason that in the second embodiment illustrated inFIG. 2, two generally parallel paths of transport for test trays areprovided for the section of the tray transport path extending from theunloader section 8 to the loader section 7 and that the unloader section8 provides for halting four test trays in all, two test trays at each ofthe first and second positions A and B while the loader section 7provides for halting two test trays therein.

[0152] This arrangement increases the number of tested ICs present inthe unloader section 8 by a factor of two as compared to the prior artIC tester to thereby permit the transporting and handling mechanismincluding the X-Y transport 81 to transfer tested ICs efficiently. Inaddition, as there are two test trays standing at rest in the loadersection 7, the transporting and handling mechanism including the X-Ytransport is capable of transferring ICs under test from two universaltrays loaded with ICs under test and held at the universal tray setposition 12 in the loader section 7 onto the two test trays in anefficient manner. Consequently, this arrangement produces the advantageof reducing the testing time of the IC tester as a whole.

[0153] The advantages of the second embodiment described above will nowbe explained on the basis of specific numeral values concerning theunloader section 8 with reference to FIG. 3.

[0154]FIG. 3 illustrates the categories of sixty-four tested ICs placedon a test tray 3 at a standstill in the unloader section 8.Specifically, FIG. 3(a) illustrates the case where there is one path oftransport for test trays for the section of the tray transport pathextending from the unloader section 8 to the loader section 7, as is thecase with the prior art IC tester whereas FIG. 3(b) illustrates the casewhere there are two paths of transport for test trays for the section ofthe tray transport path extending from the unloader section 8 to theloader section 7. While in the case of FIG. 3(b) two test trays are bothshown as having tested ICs of like categories placed in like positions,this is only an example. It will be obvious to one skilled in the artthat the positions allotted to the various categories may often varyfrom one tray to another.

[0155] As is apparent from FIG. 3, in this example most of the testedICs placed on one test tray 3 belong to the category 1 with a few ICsbelong to the categories 2 and 3 (the numerals 1, 2 and 3 marked in thetest tray 3 representing the categories).

[0156] The movable head of the X-Y transport is provided with fourpickup pads. Except for the number of transporting travels for thetested ICs of the category 1, the transporting travel of the movablehead of the X-Y transport is executed two times in total, one for eachof the tested ICs of the categories 2 and 3 in the case of FIG. 3(a).Likewise in the case of FIG. 3(b), since two test trays 3 are at astandstill in the first position A, the movable head makes twotransporting travels in total, one for each of the tested ICs of thecategories 2 and 3.

[0157] As noted above, the number of transporting travels of the movablehead is equally two for the tested ICs of the categories 2 and 3 both inthe case of FIG. 3(a) and in the case of FIG. 3(b). It should be notedthat there are only one test trays at a standstill in the case of FIG.3(a) whereas in the case of FIG. 3(b) there are two test trays at astandstill. Otherwise stated, in the case of FIG. 3(a) since the sametransporting motions are repeated for two test trays, the total numberof transporting travels of the movable head amounts to four, that is,twice the total number of transporting travels in the case of FIG. 3(b).It will thus be appreciated that the IC tester according to the secondembodiment described above improves the transporting efficiency in theunloader section 8 by a factor of two.

[0158] If the number of categories of tested ICs is further increased,there may be more categories of tested ICs than the number of universaltrays held at the universal tray set position 12 in the unloader section8. As already explained, such instance necessitates the operation ofreplacing universal trays in which some of the universal trays locatedin the universal tray set position 1 2 are returned to the storagesection 11 and in replacement, the universal trays for the correspondingcategory or categories. This replacement operation, however, takes aconsiderably long time, leading to the problem of prolonging the testingtime.

[0159] In order to minimize the required frequency of universal trayreplacement, it is preferable that as many tested ICs as possible bedisposed in the unloader section 8. For, in the case that there are notmany tested ICs placed on the test trays at rest in the unloader section8, if the operation of replacing universal trays is required to sort andhandle tested ICs placed on a first test tray, then there is a highlikelihood that the universal tray replacing operation may benecessitated also to sort and handle tested ICs placed on a second testtray.

[0160] Incidentally, if the number of tested ICs placed on a test tray 3is doubled, it is presumed that the required frequency of universal trayreplacement may be reduced by half. As indicated hereinbefore, doublingthe loading capacity of the test tray 3 by simply doubling the externalsize of the test tray in the Y-axis dimension while retaining theexternal size in the X-axis dimension as such would be accompanied withthe various problems as mentioned above. However, when as in the secondembodiment two paths of transport for test trays are provided for thesection of the transport path extending from the unloader section 8 tothe loader section 7 so that two test trays may be simultaneouslytransported, two test trays naturally provide twice the loading capacityof one test tray, and yet none of the aforementioned various problemsoccur. Besides, additional advantages are provided that theconfiguration and size of the constant temperature chamber 4 and theexit chamber 5 is not affected in any way and that the conventional testtray may be employed as such.

[0161] The operation of the IC tester constructed according to thesecond embodiment described above will now be briefly explained. ICs tobe tested are transferred from universal trays onto two test trays at astandstill in the first transport path (the upper transport path asviewed in the drawing) and the second transport path (the lowertransport path as viewed in the drawing), respectively in the loadersection 7. When the test tray in the first transport path is filled, itis conveyed into the soak chamber 41 to be placed on the uppermost testtray supporting stage of the vertical transport mechanism in the soakchamber. Once the newly received test tray has been lowered to the nextlower test tray supporting stage by the vertical transport mechanism,the next test tray filled with ICs to be tested is conveyed from thesecond transport path into the soak chamber 41 to be placed on theuppermost test tray supporting stage of the vertical transportmechanism.

[0162] When both of the two transport paths in the loader section 7 aredepleted of the test trays, two test trays emptied subsequent tocompletion of the sorting operation of tested ICs are transported fromthe unloader section 8 to the loader section 7. When the second positionB in the unloader section 8 is vacated, two test trays at rest at thefirst position A are transported through the two respective transportpaths from the first positions A to the second position B subsequent tocompletion of the sorting operation at the first position A. Upondepletion of the test trays from both of the two transport paths in theunloader section 8, test trays loaded with tested ICs relieved ofheat/cold are delivered from the uppermost test tray supporting stage ofthe vertical transport mechanism in the exit chamber 5 to the firstposition A in the second transport path in the unloader section 8,whereafter test trays loaded with tested ICs as newly raised to theuppermost test tray supporting stage of the vertical transport mechanismin the exit chamber 5 are discharged to the first position A in thefirst transport path in the unloader section 8.

[0163] The operation of the vertical transport mechanism in the soakchamber 41, the testing (measurement) in the testing section 42, theoperation of the vertical transport mechanism in the exit chamber 5,etc. are identical to those in the prior art IC tester shown in FIG. 11,and further description is omitted. In this embodiment as well, aposition corrector 2 for correcting the orientation or position of an ICcalled “preciser” is located between the universal tray set position 12and the stop position for the test tray 3. The function of this ICposition corrector 2 has already been described hereinbefore, andfurther description is omitted.

[0164] Further, the sorting operation, the universal tray replacementoperations , etc. in the unloader section 8 are also essentially thesame as in the prior art IC tester shown in FIG. 11 except that thenumber of test trays handled is doubled, and will not be describedrepeatedly. It should only be noted that as an alternative arrangement,separate X-Y transports may be provided for the first and secondpositions A and B to further enhance the rate of handling tested ICs. Inaddition, the IC accommodating capacity of the buffer 6 disposed betweenthe stop positions A and B for the test tray and the locations of theuniversal trays 1 a-1 d may be increased so as to the number of testedICs which can be temporarily kept in the buffer section 6.

[0165] As in the illustrated prior art IC tester, a tray transport,although not shown in FIG. 2, is disposed above the IC-to-be-testedstorage racks and the tested-IC storage racks for movement over theentire extent of those storage racks in the direction of arrangement ofthe racks (in the X-axis direction). The operation of this traytransport has already been described before, and no further descriptionis repeated here.

[0166] In the construction according to the second embodiment described,while there is only one path of transport for the test tray running fromthe loader section 7 through the soak chamber 41 and the testing section42 in the constant temperature chamber 4 and the exit chamber 5 to theunloader section 8 as in the illustrated prior art IC tester, two suchpaths are provided for the transport from the unloader section 8 to theloader section 7. It is thus to be understood that this constructionpermits four test trays in all, two for each of the first and secondstop positions A and B in the unloader section 8 to be halted, despitethe fact that the conventional test trays are used as such. Accordingly,the presence of twice as many as tested ICs as in the prior art in theunloader section 8 permits the transporting and handling mechanismincluding the X-Y transport 81 to transport tested ICs more efficientlyto thereby increase the throughput in number of tested ICs. Further,because of two test trays waiting in the loader section 7, thetransporting and handling mechanism including the X-Y transport 71 isenabled to transfer ICs to be from universal trays onto the test traysin an efficient manner whereby the throughput in number of ICs to betested may be enhanced. In this way, this arrangement also provides theadvantage of reducing the testing time of the IC tester as a whole andgreatly cutting the testing cost per IC.

[0167] In addition, in the construction according to the secondembodiment described above as well, the overall size of the IC testerneed be enlarged only in depth by only about one length of the minoredge of the test tray in order to provide two paths of test traytransport extending from the soak chamber 41 through the testing section42 to the exit chamber 5. Consequently, the advantages are obtained thatthe depth dimension of the entire IC tester may be made considerablysmaller and that the apparatus may be manufactured less expensively, ascompared to the construction which would result if in the prior art ICtester shown in FIG. 11 two of the arrangement comprising the unloadersection 8 and the loader section 7 were provided in order to establishtwo paths of test tray transport extending from the unloader section 8to the loader section 7.

[0168] As discussed above, the provision of two paths of test traytransport for the section of the path running from the soak chamber 41through the testing section 42 to the exit chamber 5 in the firstembodiment and for the section of the path extending from the unloadersection 8 to the loader section 7 in the second embodiment, respectivelymake it possible to increase the simultaneous measurement throughput innumber of ICs in the first embodiment and the number of ICs handled perunit time in the unloader section 8 and the loader section 7 in thesecond embodiment, respectively, even by the use of conventional testtrays in both cases. It is noted, however, that the provision of twopaths of test tray transport necessitates one independent drive meansfor each of the transport paths.

[0169]FIG. 4 illustrates a third embodiment of the present invention inwhich the depth (length in the Y-axis direction) of the constanttemperature chamber 4 and the exit chamber 5 is expanded as compared tothe prior art IC tester by a dimension corresponding approximately toone transverse width (length of the minor edge) of the rectangular testtray 3 and in which a single widened path of transport for test trays isprovided for the section of path extending from and through the soakchamber 41 and the testing section 42 in the constant temperaturechamber 4 to and through the exit chamber 5 so that two test trays inengagement with each other, that is, in a state integrally joinedtogether may be transported along the two paths of transport, wherebythe need for providing two independent drive means for the test traytransport path.

[0170] In this third embodiment as well, the width (length in the Y-axisdirection) of the widened path of transport is approximately equal tothe sum of transverse widths of two test trays, so that the widened pathincreases the depth (length in the Y-axis direction) of the IC testeronly by a dimension corresponding approximately to the length of theminor edge of the test tray 3. It is to be noted that in FIG. 4 the likeparts and elements corresponding to those of FIG. 11 are designated bythe same reference numerals and will not be discussed again in details,unless required.

[0171] Like the IC tester shown in FIG. 1, the IC tester illustrated inFIG. 4 is configured such that the constant temperature chamber 4including the soak chamber 41 and testing section 42, and the exitchamber 5 are arranged in the left to right direction as viewed in thedrawing (referred to as X-axis direction herein) in the rear portion ofthe IC tester while in front of the constant temperature chamber 4 andthe exit chamber 5 there are located the loader section 7 and unloadersection 8. The loader section 7 is adapted for transferring andreloading ICs under test onto test trays 3 capable of withstandinghigh/low temperatures while the unloader section 8 is adapted fortransferring and reloading tested ICs which have been carried on thetest tray 3 out through the exit chamber 5 subsequently to being testedin the testing section 42 of the constant temperature chamber 4 from thetest tray 3 to the universal tray. Further, in the forefront of the ICtester there is located a storage section 11 for storing universal trays1 loaded with ICs to be tested and universal trays 1 loaded with ICsalready tested and sorted.

[0172] More specifically, the soak chamber 41, the testing section 42,and the exit chamber 5 are arranged in the order named from left toright in the X-axis direction in the drawing, and the loader section 7and the unloader section 8 are located in front of the soak chamber 41of the constant temperature chamber 4 and in front of the exit chamber5, respectively. Accordingly, as in the conventional IC tester, the testtray 3 is delivered into the constant temperature chamber 4 in thedirection (Y-axis direction) which is perpendicular to the direction(X-axis direction) in which it has been conveyed from the unloadersection 8 to the loader section 7. From the constant temperature chamber4, the test tray 3 is again delivered out in the direction which isperpendicular to the direction in which it has been introduced from theloader section 7. Likewise, from the exit chamber 5, the test tray 3 isdelivered out in the direction which is perpendicular to the directionin which it has been introduced from the constant temperature chamber 4.From the unloader section 8, the test tray 3 is again discharged in thedirection which is perpendicular to the direction in which it has beenintroduced from the exit chamber 5.

[0173] The test tray 3 may be of the same size and construction as thatused with the conventional IC tester already described with reference toFIG. 11. That is, the test tray 3 has the construction as shown in FIG.12. The test tray 3 is moved in a circulating manner from and back tothe loader section 7 sequentially through the soak chamber 41 and thetesting section 42 in the constant temperature chamber 4, the exitchamber 5, and the unloader section 8. In this path of circulatingtravel, there are disposed a predetermined number of test trays 3 whichare successively moved in the directions as indicated by thickcross-hatched arrows in FIG. 1 by a test tray transport.

[0174] In this third embodiment of the invention, the depth (length inthe Y-axis direction) of the constant temperature chamber 4 and the exitchamber 5 is expanded as compared to the prior art IC tester by adimension corresponding approximately to one transverse width (length ofthe minor edge) of the rectangular test tray 3, and the width of thetest tray transport path extending from the soak chamber 41 in theconstant temperature chamber 4 through the testing section 42 in theconstant temperature chamber 4 to the exit chamber 5 is madeapproximately equal to the sum of transverse widths of two test trays sothat two test trays with their opposing major edges in engagement witheach other as shown may be simultaneously transported.

[0175] The operation of the IC tester constructed as described justabove will now be explained.

[0176] A test tray 3 having ICs under test loaded thereon from auniversal tray 1 in the loader section 7 is conveyed with one of itsmajor edges in the front from the loader section 7 to the constanttemperature chamber 4 and is introduced into the soak chamber 41 throughan inlet formed in the front side of the constant temperature chamber 4The soak chamber 41 is equipped therein with a vertical transportmechanism adapted to support a plurality of (say, five) test trays 3stacked one on another with predetermined spacings therebetween.

[0177] In this embodiment, each stage of the vertical transportmechanism for supporting test trays thereon has a depth approximatelyequal to the sum of transverse widths of two test trays. The first testtray 3 received from the loader section 7 is placed and supported on theuppermost stage of the vertical transport mechanism in the back halfsection (the upper half section as viewed in the Y-axis direction) ofthat stage. The vertical transport mechanism is at a standstill untiltwo test trays are transported onto the uppermost stage. Once the secondtest tray 3 has been transported from the loader section 7 onto theuppermost stage of the vertical transport mechanism and accommodated inthe front half section (the lower half section as viewed in the Y-axisdirection) of the stage in abutment and engagement with the first testtray, the vertical transport mechanism is actuated to move the testtrays on the successive stages downwardly by one stage in the verticaldirection (which is referred to Z-axis direction). Alternatively, thearrangement may be such that after the first test tray has been placedinto the back half section on the uppermost stage of the verticaltransport mechanism, the vertically downward movement of the verticaltransport mechanism is stopped until the lapse of a predetermined periodof time.

[0178] The vertical transport mechanism is configured to support twotest trays with their opposing major edges in engagement with each otheron each stage, that is, to support two test trays in a state integrallyjoined together, and is operative to move the two integrally joined testtrays on each stage down successively to the next lower stage.

[0179] While two test trays on the uppermost stage are moved downthrough the successive stages to the lowermost stage, and during awaiting time until the testing section 42 is vacated (available for nexttesting), the ICs to be tested on the two integrally joined test traysare loaded with a temperature stress of either a predetermined high orlow temperature. Once the two test trays have been moved down to thelowermost stage, they, while in the integrally joined state, aresimultaneously delivered out along the respective paths of transportthrough the outlet of the soak chamber 41 into the testing section 42which on the left-hand side in the X-axis direction, adjoins andcommunicates with the lower portion of the soak chamber 41. It is thuswill be appreciated that the two test trays are delivered out of thesoak chamber 41 in a direction perpendicular to the direction ofintroduction thereinto.

[0180] The testing section 42 is equipped with a single tester head (notshown) disposed at the corresponding position below the path oftransport for two integrally joined test trays. Mounted on the top ofthis tester head (performance board) are device sockets (not shown) atpredetermined positions underlying the corresponding test trays. The twointegrally joined test trays almost simultaneously delivered out of thesoak chamber 41 are transported to over these device sockets, and then apredetermined number of ICs under test out of those loaded on the testtrays are brought into electrical contact with the corresponding devicesockets mounted on the tester head while the ICs are placed on the testtrays.

[0181] Upon completion of testing on all of the ICs on the twointegrally joined test trays through the tester head, those two testtrays, while in the integrally joined state, are transported to theright in X- axis direction from the testing section 42 to the exitchamber 5 where the tested ICs are relieved of heat or cold.

[0182] It is to be noted that two tester heads, one associated with eachof the two integrally joined test trays may be provided at predeterminedpositions underlying the test tray transport path. Those tester headsmay have mounted thereon device sockets adapted to contact with the ICson the two test trays corresponding to the two tester heads.

[0183] Like the soak chamber 41, the exit chamber 5 is also equippedwith a vertical transport mechanism adapted to support a plurality of(say, five) test trays 3 stacked one on another with predeterminedspacings therebetween.

[0184] In this embodiment, each stage of the vertical transportmechanism for supporting test trays thereon in the exit chamber 5 has aninlet sized to be approximately equal to the sum of transverse widths oftwo test trays and approximately equal to one length of the major edgeof the test tray (corresponding to the dimension of the inlet of theexit chamber 5 as measured in the Y-axis direction) and a depthapproximately equal to one length of the major edge of the test tray(corresponding to the dimension of the outlet of the exit chamber 5 asmeasured in the X-axis direction). Two test trays in the integrallyjoined state introduced along the path of transport from the testingsection 42 are placed on and supported by the lowermost stage of thevertical transport mechanism.

[0185] Once two test trays in the integrally joined state have beentransported from the testing section 42 onto the lowermost stage of thevertical transport mechanism, the vertical transport mechanism isactuated to move the test trays on the successive stages upwardly by onestage in the vertical direction. While two integrally joined test trayson the lowermost stage are moved up to the uppermost stage by the upwardmovement of the successive stages by actuation of the vertical transportmechanism, the tested ICs are relieved of either heat or cold to berestored to the outside temperature (room temperature).

[0186] As already noted, since the IC test is conducted on ICs havingany desired temperature stress in a wide range of temperatures such asfrom −55° C. to +125° C. imposed thereon in the soak chamber 41, theexit chamber 5 cools the ICs with forced air down to the roomtemperature if the ICs have had a high temperature of, say, about 120°C. applied thereto in the soak chamber 41. If ICs have had a lowtemperature of, say, about −30° C. applied thereto in the soak chamber41, the exit chamber 5 heats them with heated air or a heater up to atemperature at which no condensation occurs.

[0187] After the heat removal or cold removal process, the test traylocated on the front half section of the uppermost stage of the verticaltransport mechanism is conveyed from the exit chamber 5 to the positionA at the unloader section 8 through the outlet of the exit chamberextending in the direction (facing on the front of the exit chamber 5)perpendicular to that in which it has been introduced from the testingsection 42 into the exit chamber 5. Disposed closest to the firstposition A are universal trays 1 a and 1 b. Assuming that classificationcategories 1 and 2 are allotted to these universal trays 1 a and 1 b,respectively, while the test tray 3 is stopped at the first position A,only the tested ICs belonging to the categories 1 and 2 are picked upfrom the test tray 3 held at the first position A, and transferred ontothe corresponding universal trays 1 a and 1 b, respectively. Once thetest tray 3 at rest at the first position A has been depleted of the ICsbelonging to the categories 1 and 2, the test tray is moved to thesecond position B.

[0188] Arranged closest to the second position B are universal trays 1 cand 1 d. Assuming that classification categories 3 and 4 are allotted tothese universal trays 1 c and 1 d, respectively, the tested ICsbelonging to the categories 3 and 4 are picked up from the test tray 3held at the second position B and transferred onto the correspondinguniversal trays 1 c and 1 d, respectively.

[0189] Next, the other test tray 3 located on the back half section ofthe uppermost stage of the vertical transport mechanism is conveyed fromthe exit chamber 5 through the outlet thereof to the position A at theunloader section 8 and is halted at that position. The conveyance of thefirst test tray to the unloader section 8 takes place eitherconcurrently with or after the conveyance of the preceding test trayfrom the position A to the position of the unloader section 8.

[0190] In this embodiment as well, it is noted that the number ofuniversal trays 1 that can be installed at the universal tray setpositions 12 in the unloader section 8 is limited to four by the spaceavailable. Hence, the number of categories into which ICs can be sortedin real time operation is limited to four categories 1 to 4 as notedabove. While four categories would generally be sufficient to coverthree categories for subclassifying “conforming articles” into high,medium and low response speed elements in addition to one categoryallotted to “non-conforming article,” in some instances there may besome among the tested ICs which do not belong to any of thesecategories. Should there be found any tested ICs which should beclassified into a category other than the four categories, a universaltray 1 assigned to the additional category should be taken from theempty tray storage rack 1E (the lower right corner area in FIG. 1) ofthe IC storage section 11 and be transported into the unloader section 8to store the ICs of the additional category. When this is to be done, itis also needed to transport any one of the universal trays positioned inthe unloader section 8 to the IC storage section 11 for storage therein.

[0191] If the replacement of the universal trays is effected in thecourse of the sorting operation, the latter operation would have to beinterrupted during the replacement. For this reason, this embodimentalso disposes a buffer section 6 between the stop positions A and B forthe test tray 3 and the locations of the universal trays 1 a-1 d fortemporarily keeping the tested ICs belonging to a category of rareoccurrence.

[0192] The buffer section 6 may have a capacity of accommodating, sayabout twenty to thirty ICs and be equipped with a memory portion forstoring the category and locations of ICs placed in the individual ICpockets of the buffer section 6. With this arrangement, between thesorting operations or upon the buffer section 6 being filled with ICs, auniversal tray for the category to which the ICs kept in the buffersection belong is carried from the IC storage section 1 1 to theuniversal tray set position 12 at the unloader section 8 to store theICs in that universal tray. It should be noted that ICs temporarily keptin the buffer section 6 may be scattered over a plurality of categories.In that case, it would be required to transport as many universal traysas the number of categories at a time from the IC storage section 11 tothe unloader section 8.

[0193] The test tray 3 emptied in the unloader section 8 is deliveredback to the loader section 7 where it is again loaded with ICs beingtested from the universal tray 1 to repeat the same steps of operation.

[0194] The IC transport 71 for transferring ICs from the universal tray1 to the test tray 3 in the loader section 7 may be of the sameconstruction as that used with the conventional IC tester alreadydescribed, and may comprise a pair of opposed parallel rails 71A, 71Bmounted over the loader section 7 at the ends thereof opposed in theX-axis direction and extending in the Y-axis direction, a movable arm71C spanning and mounted at opposite ends on the pair of rails 71A, 71Bfor movement in the Y-axis direction, and a movable head, not shown(pick-and-place head) carried on the movable arm 71C for movementtherealong longitudinally of the arm, that is, in the X-axis direction.

[0195] The movable head has an IC pick-up pad (IC grasping member)vertically movably mounted on its bottom surface. The movement of themovable head in the X-Y-axis directions and the downward movement of thepick-up pad bring the pick-up pad into abutment with the ICs placed onthe universal tray 1 at rest at the universal tray set position 12 toattract and grasp them by vacuum suction, for instance for transfer fromthe universal tray 1 to the test tray 3. The movable head may beprovided with a plurality of, say, eight pick-up pads so that eight ICsat a time may be transported from the universal tray 1 to the test tray3.

[0196] The unloader section 8 is also equipped with an X-Y transport 81which is identical in construction to the X-Y transport 71 provided forthe loader section 7. The X-Y transport 81 is mounted spanning the firstposition A and the second position B and performs to transship thetested ICs from the test tray 3 delivered out to the positions A and Bin the unloader section 8 onto the corresponding universal tray.

[0197] The X-Y transport 81 comprises a pair of spaced parallel rails81A, 81B mounted over the unloader section 8 at the ends thereof opposedin the X-axis direction and extending in the Y-axis direction, a movablearm 81C spanning and mounted at opposite ends on the pair of rails 81A,81B for movement in the Y-axis direction, and a movable head, not shown(pick-and-place head) carried on the movable arm 71C for movementtherealong longitudinally of the arm, that is, in the X-axis direction.

[0198] In this third embodiment as well, a position corrector 2 forcorrecting the orientation or position of an IC called “preciser” islocated between the universal tray set position 12 and the stop positionfor the test tray 3. The function of this IC position corrector 2 hasalready been described hereinbefore, and further description is omitted.

[0199] As in the illustrated prior art IC tester, a tray transport,although not shown in FIG. 4, is disposed above the IC-to-be-testedstorage racks and the tested-IC storage racks for movement over theentire extent of those storage racks in the direction of arrangement ofthe racks (in the X-axis direction). There have already been describedhereinabove the various operations of this tray transport including theoperation of holding a universal tray 1 loaded with ICs under test atthe universal tray set position in the loader section 7, the operationof holding four empty universal trays 1 a-1 d at the respectiveuniversal tray set positions 12 in the unloader section 8, the operationof storing a fully filled universal tray in the corresponding traystorage position, and the operation of, in the event that there may befound any tested IC which does not belong to any of the categoriesallotted to the designated universal trays held at the set positions 12,transporting to the set position in the unloader section 8 a universaltray for storing such IC of an other al category. Therefore, suchdescription is not repeated here.

[0200] With the construction described above, while test trays aretransported one by one in the section of the test tray transport pathrunning from the exit chamber 5 through the unloader section 8 to thesoak chamber 41 as in the illustrated prior art IC tester, two testtrays in an integrally joined state are transported along a widened pathin the section of the test tray transport path extending from the soakchamber 41 through the testing section 42 to the exit chamber 5. It isthus to be appreciated that this permits ICs under test placed on twotest trays to be simultaneously tested in the testing section 42 inspite of the use of the conventionally used test tray as such, resultingin doubling the simultaneous measurement throughput in number of ICs.Consequently, in the case that a relatively long time is required pertest in the testing section 42, the doubled simultaneous measurementthroughput in number reduces the time required to complete the testingon all of the ICs (testing time of the IC tester) to nearly half,producing the advantage of greatly saving the testing cost per IC.

[0201] Besides, the provision of the single widened path of test traytransport in the section running from the soak chamber 41 through thetesting section 42 to the exit chamber 5 requires only one independentdrive means for transporting test trays, and needs only one set ofequipment including sensors and detecting circuit for monitoring theposition of the test tray, stop means for positioning the test tray,etc. All of this contributes to saving of the initial cost as well asthe advantage of downsizing the entire test tray transporting system.

[0202] In addition, in the construction according to the thirdembodiment described above, the overall size of the IC tester need beenlarged only in depth by only about one length of the minor edge of thetest tray. Consequently, the advantages are obtained that the depthdimension of the entire IC tester may be made considerably smaller andthat the apparatus may be manufactured less expensively, as compared tothe construction which would result if in the prior art IC tester shownin FIG. 11 two of the construction comprising the soak chamber 41, thetesting section 42 and the exit chamber 5 were provided in order toincrease the simultaneous measurement throughput in number of ICs in thetesting section 42 to the exit chamber 5.

[0203] It is noted here that in the case of the first embodiment, twotest trays are transported almost simultaneously along two independentgenerally parallel paths of transport. Each of the test tray transportsis rather bulky as it is equipped with its own equipment includingsensors and detecting circuit for monitoring the position of the testtray, stop means for positioning the test tray, etc. as stated above.Moreover, a minimal space need be provided between the two paths oftransport. In contrast, the third embodiment utilizes two test trays inan integrally joined state, and yet only one path of transport for thetest tray, thereby permitting downsizing of the test tray transport andrequiring no wasteful space. As a result, the third embodiment enablesreducing the depth (length in the Y-axis direction) of the constanttemperature chamber 4 and the exit chamber 5 as compared to the firstembodiment. It is thus to be appreciated that the construction accordingto the third embodiment provides for further reducing the depth of theentire IC tester.

[0204] In the third embodiment the depth of the constant temperaturechamber 4 and the exit chamber 5 is expanded by a dimensioncorresponding approximately to one transverse width (length of the minoredge) of the rectangular test tray 3, and the width of the test traytransport path extending from the soak chamber 41 through the testingsection 42 to the exit chamber 5 is made approximately equal to the sumof transverse widths of two test trays so that two test trays in anintegrally joined state may be simultaneously transported. However, inthe case that the time required per test in the testing section 42 isrelatively short, it is preferable that with the construction of thetest tray transport path extending from the loader section 7 through thesoak chamber 41 and the testing section 42 of the constant temperaturechamber 4 and the exit chamber 5 to the unloader section 8 beingretained as in the illustrated prior art IC tester, the depth (length inthe Y-axis direction) of the loader section 7 and the unloader section 8be expanded by a dimension corresponding approximately to one transversewidth (length of the minor edge) of the rectangular test tray 3, and thewidth of the test tray transport path extending from the unloadersection 8 to the loader section 7 be increased to be approximately equalto the sum of transverse widths of two test trays so that two test traysin an integrally joined state may be simultaneously transported.

[0205] Accordingly, the present invention contemplates a fourthembodiment, although not illustrated, in which in the constructionsimilar to the second embodiment of the invention described before withreference to FIG. 2, the width of the test tray transport path extendingfrom the unloader section 8 to the loader section 7 is expanded to beapproximately equal to the sum of transverse widths of two test trays sothat two test trays in an integrally joined state may be simultaneouslytransported as in the third embodiment described above.

[0206] In addition to the advantages obtained by the second embodiment,the construction of the fourth embodiment utilizes only one path oftransport for the test tray in the section of path extending from theunloader section 8 to the loader section 7 to permit the use of a singledrive means to transport test trays, hence requiring only one set ofequipment including sensors and detecting circuit for monitoring theposition of the test tray, stop means for positioning the test tray,etc., thereby providing the advantages of being economical anddownsizing the entire test tray transporting system as well as theadvantage of further reducing the depth of the entire IC tester ascompared to the second embodiment.

[0207] Next, the construction of two test trays engageable with eachother so as to be transported in an integrally joined state will bedescribed.

[0208]FIG. 5 is a plan view illustrating one example of the constructionof test trays integrally joinable with each other and showing two testtrays 3-1 and 3-2 in engagement with each other. Each of the test traysshown in FIG. 5 is essentially the same as the conventional test tray 3already described with reference to FIG. 12, and comprises a rectangularframe 30 having three equally spaced apart parallel cleats 31 betweenthe opposed major side frame members 30 a and 30 b of the frame, and amultiplicity of (sixty-four in this example) IC carriers 34 mountedbetween each pair of opposed cleats 31 and between each of the sideframe members 30 a and 30 b and the opposed cleats. These members areformed of the material as mentioned above.

[0209] Each of the illustrated test trays is different from theconventional test tray 3 in that the opposed major side frame members(which will be referred to simply as “major edge” hereinafter) 30 a and30 b of the rectangular frame 30 are formed with two protrusions 33A,33B and two recesses 32A, 32B, respectively. In this example, one majoredge 30 a (upper major edge as viewed in the drawing) of the frame 30 isformed with two differently shaped protrusions 33A, 33B at apredetermined spacing while the other major edge 30 b (lower major edgeas viewed in the drawing) is formed with two differently shaped recesses32A, 32B mating with the protrusions 33A, 33B, respectively at positionscorresponding to the protrusions 33A, 33B (positions generally withrespect to the central cleat 31 of the frame 30). Otherwise, theconfiguration and construction of the test tray is identical to that ofthe test tray 3 shown in FIG. 12, and the description of the other partsis omitted.

[0210] With regard to the two protrusions 33A, 33B, one 33B of them iswider than the other protrusion 33A, and the wider protrusion 33B isformed generally in the middle of the major edge 30 a while the narrowerprotrusion 33A is formed to the left in the drawing. Likewise, withregard to the two recesses 32A, 32B, one 32B of them is wider than theother recess 32A, and the wider recess 32B is formed generally in themiddle of the major edge 30 b while the narrower recess 32A is formed tothe left in the drawing. It will thus be appreciated that two test traysare configured such that the protrusions 33A, 33B of one test tray areengaged (mated) with the recesses 32A, 32B of the other test tray onlywhen the two test trays are arranged in the same orientation in the samehorizontal plane.

[0211] In addition, the dimensions of the protrusions 33A, 33B areselected to be slightly smaller than those of the recesses 32A, 32B (orthe dimensions of the recesses 32A, 32B are selected to be slightlylarger than those of the protrusions 33A, 33B) such that there is aloose fit between the protrusions 33A, 33B and the recesses 32A, 32B.

[0212] As the test tray is exposed to a wide range of temperatures suchas from −55° C. to +125° C. during the use as already noted, theexternal dimensions of the tray will be somewhat deformed due to thermalexpansion/contraction. Without a certain play in the fit between theprotrusions 33A, 33B and the recesses 32A, 32B, the test tray would notbe able to take up deformations due to thermal expansion/contraction,but would possibly be dislodged out of mating engagement and besusceptible to deleterious influences such as bending and warping. Thisis the reason for the need of some looseness in the fit between theprotrusions 33A, 33B and the recesses 32A, 32B.

[0213] As will be readily appreciated from FIG. 5, in the illustratedexample each of the recesses 32A, 32B has its right side wall extendinggenerally perpendicularly inwardly but its left side wall extendingobliquely at an angle greater than 90° while each of the protrusions33A, 33B has its left side wall extending generally perpendicularlyoutwardly but its right side wall terminating in a rounded outer endcorner. Consequently, when the protrusions 33A, 33B of one tray 3-1 arefitted in the recesses 32A, 32B of the other tray 3-2, there will beclearances to the left side of the protrusions 33A, 33B as is seen inFIG. 5 while at the right hand top of the protrusions 33A, 33B willthere be also small clearances though not clearly seen in FIG. 5. Itwill thus be understood that such looseness in the fit between theprotrusions 33A, 33B and the recesses 32A, 32B adequately accommodatesany deformations (thermal expansion/contraction) due to changes intemperature.

[0214]FIG. 6 is a side view illustrating the guide members of oneexample of the transport for transporting two test trays 3-1, 3-2 in anintegrally joined state. The opposite major edges 30 a, 30 b of eachtest tray are formed with thin-walled extensions or flanges 30 c, 30 d,respectively extending outwardly and flush with the top surface of theframe 30. Two protrusions 33A, 33B are formed on the extension 30 c ofthe major edge 30 a while two recesses 32A, 32B are formed in theextension 30d of the major edge 30 b. In the illustrated example, twoprotrusions 33A, 33B only remain as the thin-walled extension 30 c ofthe major edge 30 a while the thin-walled extension 30 d of the majoredge 30 b remains except for two recesses 32A, 32B. In other words, thethin-walled extension 30d of the major edge 30 b are left as threeseparated thin-walled extension portions 30d by forming two recesses32A, 32B.

[0215] As shown in FIG. 6, a pair of opposed guide members G1, G2 havinga rectangular cross-section are disposed in parallel so as to be insliding engagement with the side surfaces of the major edges 30 a, 30 bat the opposite ends of two integrally joined test trays 3-1, 3-2 (majoredge 30 a of one test tray 3-1 and major edge 30 b of the other testtray 3-2) and the undersurfaces of the thin-walled extensions 30 c, 30d, respectively along the sections of the test tray transport pathextending from the exit of the soak chamber 41 to the inlet of thetesting section 42 and from the exit of the testing section 42 to theinlet of the exit chamber 5 in the third embodiment illustrated in FIG.4, and along the section of the test tray transport path extending fromthe first position A in the unloader section 8 to the loader section 7in the fourth embodiment, not illustrated, respectively. Supportmembers, although not shown, are additionally disposed for supportingthe undersurfaces of the test trays 3-1, 3-2.

[0216] In this way it will be readily appreciated that the pair of guidemembers G1, G2 disposed in parallel along the test tray transport pathfacilitates transporting two test trays 3-1, 3-2 while being integrallyjoined together by a single drive means from the exit of the soakchamber 41 to the inlet of the testing section 42 and then from the exitof the testing section 42 to the inlet of the exit chamber 5, or fromthe unloader section 8 to the loader section 7.

[0217] Although not illustrated, it is also to be appreciated thatengagement (fitting) and disengagement of two test trays may befacilitated if the uppermost test tray supporting stage of the verticaltransport mechanism in the soak chamber 41 is provided with a pair ofguide members in sliding contact with the side surfaces of the opposedminor edges of each test tray as introduced from the loader section 7and likewise the uppermost test tray supporting stage of the verticaltransport mechanism in the exit chamber 5 is provided with a pair ofguide members in sliding contact with the side surfaces of the opposedminor edges of each test tray. It is also to be noted that a pair ofguide members slidingly engageable with the side surfaces of the opposedminor edges of each test tray may be provided if two test trays are tobe engaged (mated) with each other at the. position A in the unloadersection 8 and likewise if two test trays in an integrally joined stateare to be disengaged from each other in the loader section 7. In suchinstance, in the unloader section 8 the guide member closer to thesecond position B is arranged to be movable so that it may be moved outof the way not to interfere with two test trays in an integrally joinedstate as they advance to the second position B. Likewise, in the loadersection 7 the guide member closer to the second position B is arrangedto be movable so that it may be moved out of the way not to interferewith two test trays in an integrally joined state as they move from thesecond position B to the loader section 7.

[0218] When the test tray of the construction shown in FIG. 5 and thetest tray transport described above are used in the third embodimentillustrated in FIG. 4, it will be easily appreciated that the first testtray 3 introduced from the loader section 7 is placed into the back halfsection of the uppermost test tray supporting stage of the verticaltransport mechanism in the soak chamber 41 and is halted thereon untilthe second test tray 3 is introduced from the loader section 7 and isplaced on the uppermost test tray supporting stage of the verticaltransport mechanism whereupon the protrusions 33A, 33B of the secondtest tray come into fitting engagement with the recesses 32A, 32B of thefirst test tray to join the two test trays integrally together. Then, itwill be easily understood that the two integrally joined test trays areconveyed from the lowermost supporting stage of the vertical transportmechanism along the single transport path to the testing section 42,followed by, upon completion of the testing on all of the ICs undertest, being delivered, while still in the integrally joined state, fromthe testing section 42 to the exit chamber 5 whence after the heatremoval or cold removal process, the test trays are transportedsuccessively one by one to the unloader section 8.

[0219] In a like manner, when the test tray of the construction shown inFIG. 5 and the test tray transport described above are used in thefourth embodiment, it will be easily appreciated that two of the testtrays delivered successively one by one from the uppermost test traysupporting stage of the vertical transport mechanism in the exit chamber5 to the first position A in the unloader section 8 united together intoone by the protrusions 33A, 33B of the succeeding test tray fitting intothe recesses 32A, 32B of the first discharged test tray. Then, uponcompletion of the sorting operation at the first position A, the twotest trays are conveyed, while in the integrally joined state, from thefirst position A to the second position B where the sorting operation iscompleted prior to being conveyed, while still in the integrally joinedstate, from the second position B to the loader section 7.

[0220] It will be obvious to those skilled in the art that theconfiguration and number of the protrusions and recesses formed in eachtest tray may be arbitrarily varied and that the manner in which twotest trays in the integrally joined state are supported by a pair ofguide members Gi, G2 is not limited to the illustrated embodiment.

[0221] FIGS. 7A-7D are plan view and perspective views illustratingseveral other modified forms of the construction of integrally joinabletest trays. In FIG. 7A, one major edge 30 a (upper major edge as viewedin the drawing) of the frame 30 is provided with two outwardlyprotruding guide pins 61A, 61B at a predetermined spacing while theother major edge 30 b (lower major edge as viewed in the drawing) isformed with two holes 62A, 62B mating with the guide pins 61A, 61B,respectively at positions corresponding to the guide pins 61A, 61B(positions generally line symmetrical with respect to the longitudinalcentral line of the frame 30).

[0222] It will be readily appreciated that the construction describedjust above permits two test trays 3-1 and 3-2 to be integrally joinedtogether simply by bringing one preceding test tray already at astandstill in the soak chamber 41 or the unloader section 8 intoabutment against the succeeding test tray. It is also noted that thedimensions of the guide pins 61A, 61B are sized to be slightly smallerthan those of the holes 62A, 62B (or the dimensions of the holes 62A,62B are selected to be slightly larger than those of the guide pins 61A,61B) such that there is a loose fit between the guide pins 61A, 61B andthe holes 62A, 62B.

[0223]FIG. 7B illustrates a modified form in which the opposed majoredges 30 a, 30 b of each test tray are provided with dedicated latchmeans. Specifically, two engagement members 63A (one of which is visiblein the drawing) which are swingable through an angle of 90° for exampleare mounted on the top surface of one major edge 30 a (upper major edgeas viewed in the drawing) of the frame 30 at a predetermined spacing.Formed in the other major edge 30 b (lower major edge as viewed in thedrawing) at positions corresponding to pins 63D extending downwardlyfrom the undersurface of the engagement members 63A adjacent their outerends (positions generally line symmetrical with respect to thelongitudinal central line of the frame 30) are two holes 64A mating withthe pins 63D, respectively.

[0224] Each engagement member 63A is pivotted at its inner end in anassociated recess 63F formed in the one major edge 30 a for pivotalmovement over an angle range of 90° (from the horizontal position to thevertical position) and the outer end portion of the engagement member63A having the pin 63D projects outwardly beyond the outer margin of themajor edge 30 a. The holes 64A in the other major edge 30 b are providedwithin respective recesses 64F formed in that major edge 30 b. Therecesses 63F and 64F in the major edges 30 a and 30 b have a depthapproximately equal to the thickness of the engagement member 63A.

[0225] It will be readily understood that the construction describedjust above permits two test trays 3-1 and 3-2 to be integrally joinedtogether when one preceding test tray already at a standstill in thesoak chamber 41 or the unloader section 8 is brought into abutmentagainst the succeeding test tray with its (the succeeding tray's)engagement members 63A in its vertical orientation), followed bypivoting the engagement members 63A to fit their pins 63D into thecorresponding holes 64A of the succeeding test tray. It is preferablethat the dimensions of the engagement members 63A, the recesses 63F,64F, the pins 63D and the holes 64A be sized such that there is a loosefit between the engagement members 63A and the recesses 63F, 64F andbetween the pins 63D and the holes 64A.

[0226]FIG. 7C illustrates a modified form in which one major edge 30 a(upper major edge as viewed in the drawing) of the frame 30 is formedwith a thin-walled extension or flange 65 extending outwardly from andflush with the top surface of the frame 30 with two through-holes 65A,65B formed through the extension 65 at a predetermined spacing while theother major edge 30 b (lower major edge as viewed in the drawing) of theframe 30 is also formed with a thin-walled extension or flange 66extending outwardly from and flush with the bottom surface of the frame30 with two protuberances 66A, 66B formed on the extension 66 atpositions corresponding to the through-holes 65A, 65B of the one majoredge 30 a (positions generally line symmetrical with respect to thelongitudinal central line of the frame 30) so as to be engageable withthose through-holes. In this case, the thickness of the extensions 65,66 of the major edges 30 a, 30 b are sized such that the sum of thethickness of the two extensions is just equal to or slightly smallerthan the thickness of the test tray.

[0227] In the construction shown in FIG. 7C, against one preceding testtray 3-1 already at a standstill in the soak chamber 41 or the unloadersection 8 is abutted the succeeding test tray 3-2 from below so that theprotuberances 66A, 66B of the succeeding test tray are fitted into thethrough-holes 65A, 65B of the preceding test tray. It will be readilyappreciated that this permits two test trays 3-1 and 3-2 to be engagedwith each other into an integrally joined state. In this case as well,it is preferable that the dimensions of the through-holes 65A, 65B andthe protuberances 66A, 66B be sized such that there is a loose fitbetween the through-holes and the protuberances.

[0228]FIG. 7D illustrates a further modified form in which there isprovided a dedicated coupling frame 67 having a pair of openings orcompartments 68A, 68B formed at a predetermined spacing foraccommodating two test trays in engagement with each other. Thearrangement is such that two test trays 3-1 and 3-2 are accommodated inthe openings 68A, 68B of the coupling frame 67 and are transportedtogether with the coupling frame 67. In this example, each of theopenings 68A, 68B of the coupling frame 67, as partly shown in FIG. 7Ein cross-sectional view, is formed around its peripheral wall with astepped shoulder on which a flange-like extension 30 f of the frame 30of the test tray rests in interlocking manner such that a test tray isreceived in each of the openings of the coupling frame 67 with thebottom surfaces of the coupling frame 67 and the test tray substantiallyflush with each other. This construction facilitates the transportationof two test trays with their positional relation being accuratelymaintained, insuring that the operations, testing, measuring, etc. inthe various sections of the IC tester effected with a high precision.Further, the transportation per se of two test trays may be carried outpositively as they are transported in unison with the coupling frame 67.

[0229] In the first to fourth embodiments described above, the presentinvention is applied to the IC tester of the type in which a constanttemperature chamber 4 including a soak chamber 41 and a testing section42, and an exit chamber 5 are arranged in the left to right direction asviewed in the drawing (X-axis direction) in the rear portion of the ICtester while in front of the constant temperature chamber 4 and the exitchamber 5 there are located a loader section 7 and an unloader section8. However, it will be apparent to those skilled in the art that thepresent invention is applicable with equal advantages to the IC testerof another construction.

[0230] By way example, the present invention is applicable to the ICtester of the type in which an exit chamber 5 is disposed underneath anunloader section 8 to reduce the transverse width (length in the Y-axisdirection) of the IC tester. FIG. 8 is a schematic perspective viewillustrating the construction according to the fifth embodiment of thepresent invention.

[0231] The fifth embodiment represents an instance of constructioneither in which two paths of transport for test trays are provided forthe section of path extending from the soak chamber 41 to the testingsection 42 so that two test trays may be substantially simultaneouslytransported along the respective transport paths or in which the widthof the test tray transport path for the section extending from the soakchamber 41 to the testing section 42 is broadened to be approximatelyequal to the sum of transverse widths of two test trays so that two testtrays in an integrally joined state may be simultaneously transported.The parts and elements corresponding to those in FIGS. 1, 2, 4 and 11are designated by the like reference numerals and will not be discussedagain in details, unless required.

[0232] In the IC tester illustrated, since each of the test traysupporting stages of the vertical transport mechanism in the exitchamber 5 has a space for accommodating only one test tray, aftercompletion of the testing on all of the ICs under test loaded on twotest trays in the testing section 42, the two test trays are separatedand delivered one by one out of the testing section 42 in the directionperpendicular to that in which they have been delivered in, and aretransferred onto the lowermost stage of the vertical transport mechanismin the exit chamber 5. As the test trays 3 is moved up through thesuccessive stages by the vertical transport mechanism in the exitchamber 5 and arrives at the uppermost stage, it is introduced into theregion of the unloader section 8 where the sorting operation is effectedon the tested ICs placed on the test tray.

[0233] Further, the IC tester illustrated is configured such that oncetwo test trays have undergone the test in the testing section 42, theyare moved to a predetermined position overlying the testing section 42prior to being delivered one by one onto the lowermost stage of thevertical transport mechanism in the exit chamber 5, so that the nextsucceeding either two separate or two integrally joined test trays maybe introduced into the testing section 42 promptly after completion ofthe testing on the preceding two test trays.

[0234] In this construction, although in the section of the transportpath extending from the exit chamber 5 through the unloader section 8and the loader section 7 to the soak chamber 41, test trays aretransported one by one as in the illustrated prior art IC tester, eithertwo juxtaposed or two integrally joined test trays are transported inthe section of the transport path extending from the soak chamber 41 tothe testing section 42. It is thus to be appreciated that despite thefact that the conventionally used test tray is employed as such, thisarrangement permits the simultaneous testing or measuring of ICs undertest loaded on two test trays, resulting in doubling the simultaneousmeasurement throughput in number of ICs. Consequently, in the case thata relatively long time is required per test in the testing section 42,the doubled simultaneous measurement throughput in number reduces thetime required to complete the testing on all of the ICs (testing time ofthe IC tester) to nearly half, producing the advantage of greatly savingthe testing cost per IC.

[0235] In the fifth embodiment described above, the depth of theconstant temperature chamber 4 is expanded by a dimension correspondingapproximately to one transverse width (length of the minor edge) of therectangular test tray 3 and two paths of transport for test trays areprovided for the section of path extending from the soak chamber 41 tothe testing section 42 so that two test trays may be substantiallysimultaneously transported along the respective transport pathsindependently of each other, or alternatively the width of the test traytransport path for the section extending from the soak chamber 41 to thetesting section 42 is broadened to be approximately equal to the sum oftransverse widths of two test trays so that two test trays in anintegrally joined state may be simultaneously transported. However, inthe case that the time required per test in the testing section 42 isrelatively short, it is preferable that with the construction of thetest tray transport path extending from the loader section 7 through thesoak chamber 41 and the testing section 42 of the constant temperaturechamber 4 to the exit chamber 5 being retained as in the illustratedprior art IC tester, the depth (length in the Y-axis direction) of theloader section 7 and the unloader section 8 be expanded by a dimensioncorresponding approximately to one transverse width (length of the minoredge) of the rectangular test tray 3, and two test tray transport pathsare provided for the section of oath extending from the unloader section8 to the loader section 7 so that two test trays may be substantiallysimultaneously transported along the respective transport pathsindependently of each other.

[0236]FIGS. 9 and 10 are a schematic perspective view and a side view,with the constant temperature chamber in cross-section, respectivelyillustrating the construction according to the sixth embodiment of thepresent invention.

[0237] The IC tester of this sixth embodiment is configured such that aconstant temperature chamber 4 is equipped with a vertical transportmechanism in the interior thereof which constitutes a soak chamber 41,the top of the constant temperature chamber 4 (at the elevation of theuppermost stage of the vertical transport mechanism) comprising atesting section 42 with a tester head 9 being mounted facedown in thetop wall of the constant temperature chamber 4 while an loader section 7and an unloader section 8 are integrated together and equipped with acommon vertical transport mechanism.

[0238] In this embodiment, each stage of the vertical transportmechanism for supporting test trays thereon in the constant temperaturechamber 4 has a lateral width approximately equal to the length of themajor edge of one test tray (the X-axis dimension direction) and a depthsized to be approximately equal to the sum of transverse widths of twotest trays (length as measured in the Y-axis direction). The first testtray 3 introduced from the loader section 7 is placed on the frontapproximately half section (the lower half section as viewed in theY-axis direction) of the lowermost stage of the vertical transportmechanism. Then, the first test tray 3 is moved from the front halfsection to the back approximately half section (the upper half sectionin the Y-axis direction) of the lowermost stage in the directionperpendicular to that in which it has been introduced. Next, the secondtest tray 3 introduced from the loader section 7 is placed on the nowvacated front approximately half section of the lowermost stage of thevertical transport mechanism. When this is done, the second test tray isaccommodated in the front half section of the lowermost stage either ata small spacing from or in abutment with the first test tray.

[0239] The vertical transport mechanism is configured to support twotest trays on each stage and is operative to move the two test trays oneach stage up successively to the next upper stage.

[0240] While two test trays on the lowermost stage are moved up throughthe successive stages to the uppermost stage, the ICs to be tested onthe two test trays are loaded with a temperature stress of either apredetermined high or low temperature.

[0241] A predetermined number of ICs out of the ICs under test loaded onthe two test tray are brought into electrical contact with the ICsockets mounted on the tester head 9 while the ICs are placed on thetest trays. As noted before, the tester head 9 is electrically connectedwith the tester proper via cable 91.

[0242] Upon completion of testing, the test tray located on the fronthalf section of the uppermost stage of the vertical transport mechanismis first conveyed from the testing section 42 via the outlet of theconstant temperature chamber 4 onto the uppermost stage of the verticaltransport mechanism in the loader section 7/unloader section 8. Once thetest tray located on the front half section of the uppermost stage hasbeen delivered out, the test tray located on the back half section ismoved to the now vacated front half section.

[0243] It is to be noted that since each of the test tray supportingstages of the vertical transport mechanism in the loader section7/unloader section 8 has a space for accommodating only one test tray,the IC tester illustrated is not able to deliver the test tray loadedwith tested ICs out of the constant temperature chamber 4 until the testtray introduced onto the uppermost stage of the vertical transportmechanism in the loader section 7/unloader section 8 is moved down tothe next succeeding stage by that vertical transport mechanism.

[0244] Once the test tray introduced onto the uppermost stage of thevertical transport mechanism in the loader section 7/unloader section 8has been lowered to the next succeeding stage, the test tray as movedonto the front half section of the uppermost stage of the verticaltransport mechanism the constant temperature chamber 4 is conveyed viathe outlet of the constant temperature chamber 4 onto the uppermoststage of the vertical transport mechanism in the loader section7/unloader section 8.

[0245] Once the test tray has been lowered to the lowermost stage by thevertical transport mechanism in the loader section 7/unloader section 8,this test tray is reloaded with ICs to be tested from a universal tray1. Subsequently, the same steps will be repeated.

[0246] In this sixth embodiment, when the test trays carrying thereonICs having undergone the test in the testing section 42 are deliveredout via the outlet of the constant temperature chamber 4, as noted abovethe two test trays simultaneously subjected to the testing (measuring)are discharged one by one in two separate operations. Accordingly, it ispreferable that a buffer section (not shown) be disposed between theconstant temperature chamber 4 and the loader section 7/unloader section8 so that two test trays may be discharged simultaneously at one time tothe exterior buffer section for temporarily keeping the tested ICstherein, prior to sorting out the ICs based on the test results andtransferring them onto the corresponding universal trays, therebyreducing the overall testing (measurement) time.

[0247] Alternatively, each stage of the vertical transport mechanism inthe loader section 7/unloader section 8 may have a space large enough toaccommodate two test trays so that the stages of the vertical transportmechanism may be moved successively vertically with each stage carryingtwo test trays thereon. It will be appreciated that this arrangement mayfurther reduce the testing time and/or the handling time for tested ICs.

[0248] While two test trays on the lowermost stage are moved up throughthe successive stages to the uppermost stage, the ICs to be tested onthe two test trays are loaded with a temperature stress of either apredetermined high or low temperature.

[0249] In the first to five embodiments described above, when tworectangular test trays are transported in juxtaposition (parallel state)in the section of transport path extending from the soak chamber 41 ofthe constant temperature chamber 4 to the exit chamber 5 or in thesection of transport path extending from the soak chamber 41 of theconstant temperature chamber 4 to the testing section 42 or in thesection of transport path extending from the unloader section 8 to theloader section 7, the two rectangular test trays are illustrated asbeing transported in a sideways long orientation (with the minor edgesleading), but it will be obvious to those skilled in the art that thefunctional advantages comparable to any of the embodiments describedabove may be obtained if the arrangement is adopted in which tworectangular test trays are transported in a longitudinally longorientation (with the major edges leading) and in tandem with twoserially succeeding.

[0250] In that case, in the sixth embodiment each test tray supportingstage of the vertical transport mechanism may be sized so as toaccommodate two test trays in a longitudinally long orientation.

[0251] In the first to five embodiments as well, each test traysupporting stage of the vertical transport mechanism in the soak chamber41 and the exit chamber 5 may have a space large enough to accommodatetwo test trays in a longitudinally long orientation.

[0252] In addition, in case the IC test is conducted in the test section42 on ICs loaded on a test tray in the normal or room temperature, thetest tray 3 need not be formed of a material capable of withstandinghigh/low temperatures. Also, there are no need that the soak chamber 41and the exit chamber 5 as well as the constant temperature chamber 4 areprovided in the IC tester. As a result, in such IC tester, the test tray3 is transported from the loader section 7 to the test section 42, andafter completion of the test on all ICs loaded on the test tray, thetest tray 3 is transported from the test section 42 to the unloadersection 8. Thus, the invention described above is applied to the sectionof test tray transport path extending from the loader section 7 to thetest section 42 or the section of test tray transport path extendingfrom the loader section 7 to the unloader section 8 through the testsection 42.

[0253] As is apparent from the foregoing disclosure, despite the factthat a relatively limited increase is required of the externaldimensions of the IC, the present invention provides for increasing thesimultaneous measurement throughput in number of ICs under test by afactor of about two, or significantly increasing the simultaneousthroughput in number of tested ICs in the unloader section 8, and alsosignificantly reducing the time required to transport and handle in theloader section 7 whereby the time required to complete the testing onall of the ICs up to nearly half, thus producing the advantage ofgreatly saving the testing cost per IC.

What is claimed is:
 1. A semiconductor device testing apparatus of thetype in which semiconductor devices, loaded on a test tray, aretransported to a testing section where the semiconductor devices whileloaded on the test tray are tested and after completion of the testing,are carried out of the testing section, followed by being sorted out onthe basis of the test results, characterized in that: a plurality oftransport paths are provided for transporting test trays loaded withsemiconductor devices to said testing section.
 2. The semiconductordevice testing apparatus according to claim 1, wherein, in addition tosaid transport paths for transporting test trays loaded withsemiconductor devices to said testing section, a plurality of transportpaths are provided for transporting test trays loaded with testedsemiconductor devices out of said testing section after completion ofthe testing in said testing section.
 3. The semiconductor device testingapparatus according to claim 1, further including, in addition to saidtesting section, a loader section for transferring and reloadingsemiconductor devices onto a test tray and an unloader section forreceiving and sorting tested semiconductor devices transported from saidtesting section on the basis of the test results, and wherein: saidplurality of transport paths are provided in the section of test traytransport path extending from said loader section to said testingsection.
 4. The semiconductor device testing apparatus according toclaim 1, further including, in addition to said testing section, atemperature stress applying means for applying a temperature stress of apredetermined temperature to semiconductor devices; a heat removing/coldremoving means for removing heat or cold from semiconductor deviceshaving undergone a test in said testing section; a loader section fortransferring and reloading semiconductor devices onto a test tray; andan unloader section for receiving and sorting tested semiconductordevices transported from said testing section on the basis of the testresults, and wherein: said plurality of transport paths are provided inthe section of test tray transport path extending from said temperaturestress applying means to said testing section.
 5. The semiconductordevice testing apparatus according to claim 4, wherein said temperaturestress applying means and said testing section are located in the backportion of said semiconductor device testing apparatus while said loadersection and said unloader section are located in front of saidtemperature stress applying means and said testing section, said heatremoving/cold removing means being located in front of said testingsection and underneath said unloader section.
 6. The semiconductordevice testing apparatus according to claim 2, further including, inaddition to said testing section, a loader section for transferring andreloading semiconductor devices onto a test tray and an unloader sectionfor receiving and sorting tested semiconductor devices transported fromsaid testing section on the basis of the test results, and wherein: saidplurality of transport paths are provided in the section of test traytransport path extending from said loader section via said testingsection to said unloader section.
 7. The semiconductor device testingapparatus according to claim 2, further including, in addition to saidtesting section, a temperature stress applying means for applying atemperature stress of a predetermined temperature to semiconductordevices; a heat removing/cold removing means for removing heat or coldfrom semiconductor devices having undergone a test in said testingsection; a loader section for transferring and reloading semiconductordevices onto a test tray; and an unloader section for receiving andsorting tested semiconductor devices transported from said testingsection on the basis of the test results, wherein: said plurality oftransport paths are provided in the section of test tray transport pathextending from said temperature stress applying means via said testingsection to said heat removing/cold removing means.
 8. The semiconductordevice testing apparatus according to claim 7, wherein said temperaturestress applying means, said testing section, and said heat removing/coldremoving means are located in the back portion of said semiconductordevice testing apparatus while said loader section and said unloadersection are located in front of said temperature stress applying means,said testing section, and said heat removing/cold removing means.
 9. Thesemiconductor device testing apparatus according to any one of claims 1to 8, wherein there are two said transport paths for transporting testtrays.
 10. The semiconductor device testing apparatus according to anyone of claims 4, 5, 7 and 8, wherein said temperature stress applyingmeans is provided with a vertical transport mechanism configured tosupport a plurality of test trays in the form of a stack with apredetermined spacing between stacked two test trays, each stage of saidvertical transport mechanism for supporting test trays having a spacefor accommodating a plurality of test trays such that a plurality oftest trays introduced successively from said loader section are placedon either the uppermost or the lowermost test tray supporting stage ofsaid vertical transport mechanism successively from the back side towardthe front side of said stage with successive trays either arranged atpredetermined small spacings between adjacent trays or in abutment witheach other.
 11. The semiconductor device testing apparatus according toany one of claims 4, 5, 7 and 8, wherein there are two said transportpaths for transporting test trays, and said temperature stress applyingmeans is provided with a vertical transport mechanism configured tosupport a plurality of test trays in the form of a stack with apredetermined spacing between stacked two test trays, each stage of saidvertical transport mechanism for supporting test trays having a spacefor accommodating two test trays such that a first test tray introducedfrom said loader section is placed on either the uppermost or thelowermost test tray supporting stage of said vertical transportmechanism in the back section of said stage and a second succeeding testtray introduced from said loader section is placed on either theuppermost or the lowermost test tray supporting stage in the frontsection of said stage at a predetermined small spacing from or inabutment with said first test tray.
 12. The semiconductor device testingapparatus according to any one of claims 4, 5, 7 and 8, wherein saidheat removing/cold removing means is provided with a vertical transportmechanism configured to support a plurality of test trays in the form ofa stack with a predetermined spacing between stacked two test trays,each stage of said vertical transport mechanism for supporting testtrays having a space for accommodating a plurality of test trays suchthat a plurality of test trays introduced from said testing section areplaced as such on either the uppermost or the lowermost test traysupporting stage of said vertical transport mechanism.
 13. Thesemiconductor device testing apparatus according to any one of claims 4,5, 7 and 8, wherein there are two said transport paths for transportingtest trays, and said heat removing/cold removing means is provided witha vertical transport mechanism configured to support a plurality of testtrays in the form of a stack with a predetermined spacing betweenstacked two test trays, each stage of said vertical transport mechanismfor supporting test trays having a space for accommodating two testtrays such that two test trays introduced from said loader section areplaced as such on either the uppermost or the lowermost test traysupporting stage of said vertical transport mechanism.
 14. Asemiconductor device testing apparatus of the type including a loadersection for transferring and reloading semiconductor devices onto a testtray, and an unloader section for receiving and sorting testedsemiconductor devices on the basis of the test results, and in whichsemiconductor devices, loaded on a test tray, are transported from saidloader section to a testing section where the semiconductor deviceswhile loaded on the test tray are tested and after completion of thetesting, said tested semiconductor devices loaded on said test tray aretransported from said testing section to said unloader section, followedby being sorted out on the basis of the test results, characterized inthat: a plurality of transport paths are provided in the section of testtray transport path extending from said unloader section to said loadersection.
 15. The semiconductor device testing apparatus set forth inclaim 14, further including a temperature stress applying means forapplying a temperature stress of a predetermined temperature tosemiconductor devices and a heat removing/cold removing means forremoving heat or cold from semiconductor devices having undergone a testin said testing section, and wherein: said temperature stress applyingmeans and said testing section are located in the back portion of saidsemiconductor device testing apparatus while said loader section andsaid unloader section are located in front of said temperature stressapplying means and said testing section, said heat removing/coldremoving means being located in front of said testing section andunderneath said unloader section.
 16. The semiconductor device testingapparatus set forth in claim 14, further including a temperature stressapplying means for applying a temperature stress of a predeterminedtemperature to semiconductor devices and a heat removing/cold removingmeans for removing heat or cold from semiconductor devices havingundergone a test in said testing section, and wherein: said temperaturestress applying means, said testing section, and said heat removing/coldremoving means are located in the back portion of said semiconductordevice testing apparatus while said loader section and said unloadersection are located in front of said temperature stress applying means,said testing section, and said heat removing/cold removing means. 17.The semiconductor device testing apparatus according to any one ofclaims 14 to 16, wherein there are two said transport paths fortransporting test trays.
 18. A semiconductor device testing apparatus ofthe type in which semiconductor devices, loaded on a test tray, aretransported to a testing section where the semiconductor devices whileloaded on the test tray are tested and after completion of the testing,are carried out of the testing section, followed by being sorted out onthe basis of the test results, characterized in that: a test traytransport path for transporting test trays loaded with semiconductordevices to said testing section is a widened transport path broad enoughto transport a plurality of test trays simultaneously with saidplurality of test trays juxtaposed in a direction transverse to saidtest tray transport path.
 19. The semiconductor device testing apparatusaccording to claim 18, wherein, in addition to said test tray transportpath for transporting test trays loaded with semiconductor devices tosaid testing section, a test tray transport path for transporting testtrays loaded with tested semiconductor devices out of said testingsection after completion of the testing is a widened transport pathbroad enough to transport a plurality of test trays simultaneously withsaid plurality of test trays juxtaposed in a direction transverse tosaid test tray transport path.
 20. The semiconductor device testingapparatus according to claim 18, further including, in addition to saidtesting section, a loader section for transferring and reloadingsemiconductor devices onto a test tray and an unloader section forreceiving and sorting tested semiconductor devices transported from saidtesting section on the basis of the test results, and wherein: a testtray transport path for transporting test trays extending from saidloader section to said testing section is a widened transport path broadenough to transport a plurality of test trays simultaneously with saidplurality of test trays juxtaposed in a direction transverse to saidtest tray transport path.
 21. The semiconductor device testing apparatusaccording to claim 18, further including, in addition to said testingsection, a temperature stress applying means for applying a temperaturestress of a predetermined temperature to semiconductor devices; a heatremoving/cold removing means for removing heat or cold fromsemiconductor devices having undergone a test in said testing section; aloader section for transferring and reloading semiconductor devices ontoa test tray; and an unloader section for receiving and sorting testedsemiconductor devices transported from said testing section on the basisof the test results, and wherein: a test tray transport path fortransporting test trays extending from said temperature stress applyingmeans to said testing section is a widened transport path broad enoughto transport a plurality of test trays simultaneously with saidplurality of test trays juxtaposed in a direction transverse to saidtest tray transport path.
 22. The semiconductor device testing apparatusaccording to claim 21, wherein said temperature stress applying meansand said testing section are located in the back portion of saidsemiconductor device testing apparatus while said loader section andsaid unloader section are located in front of said temperature stressapplying means and said testing section, said heat removing/coldremoving means being located in front of said testing section andunderneath said unloader section.
 23. The semiconductor device testingapparatus according to claim 19, further including, in addition to saidtesting section, a loader section for transferring and reloadingsemiconductor devices onto a test tray and an unloader section forreceiving and sorting tested semiconductor devices transported from saidtesting section on the basis of the test results, and wherein: a testtray transporting path for transporting test trays extending from saidloader section via said testing section to said unloader section is awidened transport path broad enough to transport a plurality of testtrays simultaneously with said plurality of test trays juxtaposed in adirection transverse to said test tray transport path.
 24. Thesemiconductor device testing apparatus according to claim 19, furtherincluding, in addition to said testing section, a temperature stressapplying means for applying a temperature stress of a predeterminedtemperature to semiconductor devices; a heat removing/cold removingmeans for removing heat or cold from semiconductor devices havingundergone a test in said testing section; a loader section fortransferring and reloading semiconductor devices onto a test tray; andan unloader section for receiving and sorting tested semiconductordevices transported from said testing section on the basis of the testresults, and wherein: a test tray transporting path for transportingtest trays extending from said temperature stress applying means viasaid testing section to said heat removing/cold removing means is awidened transport path broad enough to transport a plurality of testtrays simultaneously with said plurality of test trays juxtaposed in adirection transverse to said test tray transport path.
 25. Thesemiconductor device testing apparatus according to claim 24, whereinsaid temperature stress applying means, said testing section, and saidheat removing/cold removing means are located in the back portion ofsaid semiconductor device testing apparatus while said loader sectionand said unloader section are located in front of said temperaturestress applying means, said testing section, and said heat removing/coldremoving means.
 26. The semiconductor device testing apparatus accordingto any one of claims 18 to 25, wherein said plurality of test traysjuxtaposed in a direction transverse to said test tray transport pathare in engagement with each other.
 27. The semiconductor device testingapparatus according to any one of claims 18 to 25, wherein saidplurality of test trays juxtaposed in a direction transverse to saidtest tray transport path are two and in engagement with each other. 28.The semiconductor device testing apparatus according to any one ofclaims 21, 22, 24 and 25, wherein said temperature stress applying meansis provided with a vertical transport mechanism configured to support aplurality of test trays in the form of a stack with a predeterminedspacing between stacked two test trays, each stage of said verticaltransport mechanism for supporting test trays having a space foraccommodating a plurality of test trays such that a plurality of testtrays introduced successively from said loader section are placed oneither the uppermost or the lowermost test tray supporting stage of saidvertical transport mechanism successively from the back side toward thefront side of said stage with successive trays integrally engaged witheach other.
 29. The semiconductor device testing apparatus according toany one of claims 21, 22, 24 and 25, wherein said plurality of testtrays juxtaposed in a direction transverse to said test tray transportpath are two and in engagement with each other; and said temperaturestress applying means is provided with a vertical transport mechanismconfigured to support a plurality of test trays in the form of a stackwith a predetermined spacing between stacked two test trays, each stageof said vertical transport mechanism for supporting test trays having aspace for accommodating two test trays such that a first test trayintroduced from said loader section is placed on either the uppermost orthe lowermost test tray supporting stage of said vertical transportmechanism in the back section of said stage and a second succeeding testtray introduced from said loader section is placed on either theuppermost or the lowermost test tray supporting stage in the frontsection of said stage in engagement with said first tray.
 30. Thesemiconductor device testing apparatus according to any one of claims21, 22, 24 and 25, wherein said heat removing/cold removing means isprovided with a vertical transport mechanism configured to support aplurality of test trays in the form of a stack with a predeterminedspacing between stacked two test trays, each stage of said verticaltransport mechanism for supporting test trays having a space foraccommodating a plurality of test trays such that a plurality of testtrays in juxtaposition in a direction transverse to said test traytransport path introduced from said loader section are placed as such oneither the uppermost or the lowermost test tray supporting stage of saidvertical transport mechanism.
 31. The semiconductor device testingapparatus according to any one of claims 21, 22, 24 and 25, wherein saidplurality of test trays juxtaposed in a direction transverse to saidtest tray transport path are two and in engagement with each other; andsaid heat removing/cold removing means is provided with a verticaltransport mechanism configured to support a plurality of test trays inthe form of a stack with a predetermined spacing between stacked twotest trays, each stage of said vertical transport mechanism forsupporting test trays having a space for accommodating two test trayssuch that two test trays in juxtaposition in a direction transverse tosaid test tray transport path introduced from said loader section areplaced as such on either the uppermost or the lowermost test traysupporting stage of said vertical transport mechanism.
 32. Asemiconductor device testing apparatus of the type including a loadersection for transferring and reloading semiconductor devices onto a testtray, and an unloader section for receiving and sorting testedsemiconductor devices on the basis of the test results, and in whichsemiconductor devices, loaded on a test tray, are transported from saidloader section to a testing section where the semiconductor deviceswhile loaded on the test tray are tested and after completion of thetesting, said tested semiconductor devices loaded on said test tray aretransported from said testing section to said unloader section, followedby being sorted out on the basis of the test results, characterized inthat: a test tray transport path for transporting test trays extendingfrom said unloader section to said loader section is a widened transportpath broad enough to transport a plurality of test trays simultaneouslywith said plurality of test trays juxtaposed in a direction transverseto said test tray transport path.
 33. The semiconductor device testingapparatus according to claim 32, further including a temperature stressapplying means for applying a temperature stress of a predeterminedtemperature to semiconductor devices and a heat removing/cold removingmeans for removing heat or cold from semiconductor devices havingundergone a test in said testing section, and wherein: said temperaturestress applying means and said testing section are located in the backportion of said semiconductor device testing apparatus while said loadersection and said unloader section are located in front of saidtemperature stress applying means and said testing section, and saidheat removing/cold removing means being located in front of said testingsection and underneath said unloader section.
 34. The semiconductordevice testing apparatus according to claim 32, further including atemperature stress applying means for applying a temperature stress of apredetermined temperature to semiconductor devices and a heatremoving/cold removing means for removing heat or cold fromsemiconductor devices having undergone a test in said testing section,and wherein: said temperature stress applying means, said testingsection and said heat removing/cold removing means are located in theback portion of said semiconductor device testing apparatus while saidloader section and said unloader section are located in front of saidtemperature stress applying means, said testing section and said heatremoving/cold removing means.
 35. The semiconductor device testingapparatus according to any one of claims 32 to 34, wherein saidplurality of test trays juxtaposed in a direction transverse to saidtest tray transport path are in engagement with each other.
 36. Thesemiconductor device testing apparatus according to any one of claims 32to 34, wherein said plurality of test trays juxtaposed in a directiontransverse to said test tray transport path are two and in engagementwith each other.
 37. A semiconductor device testing apparatus of thetype in which semiconductor devices, loaded on a test tray, aretransported to a testing section where the semiconductor devices whileloaded on the test tray are tested and after completion of the testing,are carried out of the testing section, followed by being sorted out onthe basis of the test results, characterized in that: said test tray isgenerally of a rectangular shape, and a test tray transport path fortransporting test trays loaded with semiconductor devices to saidtesting section is a widened transport path broad enough to transportsaid rectangular test tray with the major edge of the test tray in frontin the direction of travel of the test tray.
 38. The semiconductordevice testing apparatus according to claim 37, wherein, in addition tosaid widened transport path for transporting rectangular test traysloaded with semiconductor devices to said testing section, a test traytransport path for transporting rectangular test trays loaded withtested semiconductor devices out of said testing section aftercompletion of the testing in said testing section is a widened transportpath broad enough to transport said rectangular test tray with the majoredge of said test tray in front in the direction of travel of the testtray.
 39. The semiconductor device testing apparatus according to claim37, further including, in addition to said testing section, a loadersection for transferring and reloading semiconductor devices onto a testtray and an unloader section for receiving and sorting testedsemiconductor devices transported from said testing section on the basisof the test results, and wherein: a test tray transport path extendingfrom said loader section to said testing section is a widened transportpath broad enough to transport said rectangular test tray with the majoredge of said test tray in front in the direction of travel of the testtray.
 40. The semiconductor device testing apparatus according to claim37, further including, in addition to said testing section, atemperature stress applying means for applying a temperature stress of apredetermined temperature to semiconductor devices; a heat removing/coldremoving means for removing heat or cold from semiconductor deviceshaving undergone a test in said testing section; a loader section fortransferring and reloading semiconductor devices onto a test tray; andan unloader section for receiving and sorting tested semiconductordevices transported from said testing section on the basis of the testresults, and wherein: a test tray transport path extending from saidtemperature stress applying means to said testing section is a widenedtransport path broad enough to transport said rectangular test tray withthe major edge of said test tray in front in the direction of travel ofthe test tray.
 41. The semiconductor device testing apparatus accordingto claim 40, wherein said temperature stress applying means and saidtesting section are located in the back portion of said semiconductordevice testing apparatus while said loader section and said unloadersection are located in front of said temperature stress applying meansand said testing section, said heat removing/cold removing means beinglocated in front of said testing section and underneath said unloadersection.
 42. The semiconductor device testing apparatus according toclaim 38, further including, in addition to said testing section, aloader section for transferring and reloading semiconductor devices ontoa test tray and an unloader section for receiving and sorting testedsemiconductor devices transported from said testing section on the basisof the test results, and wherein: a test tray transport path extendingfrom said loader section via said testing section to said unloadersection is a widened transport path broad enough to transport saidrectangular test tray with the major edge of said test tray in front inthe direction of travel of the test tray.
 43. The semiconductor devicetesting apparatus according to claim 38, further including, in additionto said testing section, a temperature stress applying means forapplying a temperature stress of a predetermined temperature tosemiconductor devices; a heat removing/cold removing means for removingheat or cold from semiconductor devices having undergone a test in saidtesting section; a loader section for transferring and reloadingsemiconductor devices onto a test tray; and an unloader section forreceiving and sorting tested semiconductor devices transported from saidtesting section on the basis of the test results, and wherein: a testtray transport path extending from said temperature stress applyingmeans via said testing section to said heat removing/cold removing meansis a widened transport path broad enough to transport said rectangulartest tray with the major edge of said test tray in front in thedirection of travel of the test tray.
 44. The semiconductor devicetesting apparatus set forth in claim 43, wherein said temperature stressapplying means, said testing section, and said heat removing/coldremoving means are located in the back portion of said semiconductordevice testing apparatus while said loader section and said unloadersection are located in front of said temperature stress applying means,said testing section, and said heat removing/cold removing means. 45.The semiconductor device testing apparatus according to any one ofclaims 37 to 44, wherein a plurality of rectangular test trays aretransported at a time serially with the major edge of each of said testtrays in front in the direction of travel of the test trays along saidtest tray transport path.
 46. The semiconductor device testing apparatusaccording to any one of claims 37 to 44, wherein two rectangular testtrays are transported at a time serially with the major edge of each ofsaid test trays in front in the direction of travel of the test traysalong said test tray transport path.
 47. The semiconductor devicetesting apparatus according to any one of claims 40, 41, 43 and 44,wherein said temperature stress applying means is provided with avertical transport mechanism configured to support a plurality of testtrays in the form of a stack with a predetermined spacing betweenstacked two test trays, each stage of said vertical transport mechanismfor supporting test trays having a space for accommodating a pluralityof test trays in a row with the major edge of each of said test trays infront in the direction of travel of the test trays as said test traysare introduced from said loader section.
 48. The semiconductor devicetesting apparatus according to claim 47, wherein said plurality of testtrays introduced successively from said loader section are placed ontoeither the uppermost or the lowermost test tray supporting stage of saidvertical transport mechanism, followed by being fed successively, exceptthe last introduced test tray, in a direction perpendicular to thedirection of introduction while said last introduced test tray isretained as it has been introduced from said loader section, wherebysaid plurality of test trays are placed on either the uppermost or thelowermost test tray supporting stage of said vertical transportmechanism in juxtaposition in a row from the outlet of said temperaturestress applying means with predetermined small spacings between adjacenttrays or in abutment with each other.
 49. The semiconductor devicetesting apparatus according to claim 47, wherein each stage of saidvertical transport mechanism of said heat removing/cold removing meansfor supporting test trays has a space for accommodating two test traysin a row with the major edge of each of said test trays in front in thedirection of travel of the test trays.
 50. The semiconductor devicetesting apparatus according to any one of claims 40, 41, 43 and 44,wherein said heat removing/cold removing means is provided with avertical transport mechanism configured to support a plurality of testtrays in the form of a stack with a predetermined spacing betweenstacked two test trays, each stage of said vertical transport mechanismfor supporting test trays having a space for accommodating a pluralityof test trays in a row with the major edge of each of said test trays infront in the direction of travel of the test trays such that a pluralityof test trays serially introduced from said testing section are placedas such on either the uppermost or the lowermost test tray supportingstage of said vertical transport mechanism.
 51. The semiconductor devicetesting apparatus according to any one of claims 40, 41, 43 and 44,wherein said heat removing/cold removing means is provided with avertical transport mechanism configured to support a plurality of testtrays in the form of a stack with a predetermined spacing betweenstacked two test trays, each stage of said vertical transport mechanismfor supporting test trays having a space for accommodating two testtrays in a row with the major edge of each of said test trays in frontin the direction of travel of the test trays such that two test traysserially introduced from said testing section are placed as such oneither the uppermost or the lowermost test tray supporting stage of saidvertical transport mechanism.
 52. A semiconductor device testingapparatus of the type including a loader section for transferring andreloading semiconductor devices onto a test tray, and an unloadersection for receiving and sorting tested semiconductor devices on thebasis of the test results, and in which semiconductor devices, loaded ona test tray, are transported from said loader section to a testingsection where the semiconductor devices while loaded on the test trayare tested and after completion of the testing, said testedsemiconductor devices loaded on said test tray are transported from saidtesting section to said unloader section, followed by being sorted outon the basis of the test results, characterized in that: a test traytransport path for transporting test trays extending from said unloadersection to said loader section is a widened transport path broad enoughto transport a rectangular test tray with the major edge of said testtray in front in the direction of travel of the test tray.
 53. Thesemiconductor device testing apparatus according to claim 52, furtherincluding a temperature stress applying means for applying a temperaturestress of a predetermined temperature to semiconductor devices and aheat removing/cold removing means for removing heat or cold fromsemiconductor devices having undergone a test in said testing section,and wherein: said temperature stress applying means and said testingsection are located in the back portion of said semiconductor devicetesting apparatus while said loader section and said unloader sectionare located in front of said temperature stress applying means and saidtesting section, and said heat removing/cold removing means beinglocated in front of said testing section and underneath said unloadersection.
 54. The semiconductor device testing apparatus according toclaim 52, further including a temperature stress applying means forapplying a temperature stress of a predetermined temperature tosemiconductor devices and a heat removing/cold removing means forremoving heat or cold from semiconductor devices having undergone a testin said testing section, and wherein: said temperature stress applyingmeans, said testing section and said heat removing/cold removing meansare located in the back portion of said semiconductor device testingapparatus while said loader section and said unloader section arelocated in front of said temperature stress applying means, said testingsection and said heat removing/cold removing means.
 55. Thesemiconductor device testing apparatus according to any one of claims 52to 54, wherein a plurality of said rectangular test trays aretransported to said testing section at a time serially with the majoredge of each of said rectangular test trays in front in the direction oftravel of the test tray along said test tray transport path.
 56. Thesemiconductor device testing apparatus according to any one of claims 52to 54, wherein two of said rectangular test trays are transported tosaid testing section at a time serially with the major edge of each ofsaid rectangular test trays in front in the direction of travel of thetest tray along said test tray transport path.
 57. A semiconductordevice testing apparatus of the type in which semiconductor devices,loaded on a test tray, are transported to a testing section where thesemiconductor devices while loaded on the test tray are tested and aftercompletion of the testing, are carried out of the testing section,followed by being sorted out on the basis of the test results,characterized in that: a vertical transport mechanism configured tosupport a plurality of test trays in the form of a stack with apredetermined spacing between stacked two test trays is provided in aconstant temperature chamber containing a temperature stress applyingmeans for applying a temperature stress of a predetermined temperatureto semiconductor devices and said testing section, each stage of saidvertical transport mechanism for supporting test trays having a spacefor accommodating a plurality of test trays so that a plurality of testtrays may be simultaneously transported to said testing section.
 58. Thesemiconductor device testing apparatus according to claim 57, furtherincluding a loader section for transferring and reloading semiconductordevices onto a test tray and an unloader section for receiving andsorting tested semiconductor devices on the basis of the test results,and wherein each of said loader section and said unloader section isprovided with a vertical transport mechanism configured to support aplurality of test trays in the form of a stack with a predeterminedspacing between stacked two test trays, each stage of said verticaltransport mechanism for supporting test trays having a space foraccommodating one test tray.
 59. The semiconductor device testingapparatus set forth in claim 57, further including a loader section fortransferring and reloading semiconductor devices onto a test tray and anunloader section for receiving and sorting tested semiconductor deviceson the basis of the test results, and wherein each of said loadersection and said unloader section is provided with a vertical transportmechanism configured to support a plurality of test trays in the form ofa stack with a predetermined spacing between stacked two test trays,each stage of said vertical transport mechanism for supporting testtrays having a space for accommodating a plurality of test trays. 60.The semiconductor device testing apparatus according to any one ofclaims 57 to 59, wherein a tester head is mounted on the top of saidconstant temperature chamber, and when a plurality of test trays placedon each test tray supporting stage of said vertical transport mechanismin said constant temperature chamber are raised up to the uppermost testtray supporting stage by said vertical transport mechanism in saidconstant temperature chamber, a predetermined number of semiconductordevices out of the semiconductor devices loaded on said plurality oftest trays on the uppermost test tray supporting stage are electricallyconnectable with device sockets mounted on said tester head, with saiddevice sockets facing downwardly.
 61. The semiconductor device testingapparatus according to claim 58 or claim 59, wherein each of said stagesfor supporting test trays of said vertical transport mechanism in saidconstant temperature chamber has a space for accommodating a pluralityof test trays in a row as said test trays are introduced from saidloader section, said plurality of test trays introduced successivelyfrom said loader section are placed onto either the uppermost or thelowermost test tray supporting stage of said vertical transportmechanism in said constant temperature chamber, followed by being fedsuccessively, except the last introduced test tray, in a directionperpendicular to the direction of introduction while said lastintroduced test tray is retained as it has been introduced from saidloader section.
 62. Test trays used in said semiconductor device testingapparatus set forth in any one of claims 18 to 25 and claims 32 to 34,each of said test trays comprising a rectangular frame having one of twoopposite edges formed with recess means and the other of the oppositeedges formed with protrusion means, said test trays being integrallyjoinable with each other by said protrusion means of one of said testtrays being engaged with said recess means of another one of said testtrays.
 63. Test trays used in said semiconductor device testingapparatus set forth in any one of claims 18 to 25 and claims 32 to 34,each of said test trays comprising a rectangular frame having one of twoopposite edges provided with pivotable engagement protrusion means andthe other of the opposite edges provided with recess means engageablewith said pivotable engagement protrusion means, said test trays beingintegrally joinable with each other by said engagement protrusion meansof one of said test trays being engaged with said recess means ofanother one of said test trays.
 64. The semiconductor device testingapparatus according to any one of claims 18 to 25 and 32 to 34,characterized in that: a plate-like member of substantially square shapeis provided, said plate-like member having a pair of openings formed injuxtaposition at a predetermined spacing therebetween for accommodatingtwo test trays, one fitted in each of said openings, so that the twotest trays in unison with said plate-like member may be transportedalong said test tray transport path.